gen_seq.v

4位数字频率计的verilog HDL设计

module Gen_Seq(Latch,Catch,Clear,Clk);
 input Clk;
 output Latch;
 output Catch;
 output Clear;

 reg Latch,Catch,Clear;

 reg [1:0] Cnt1;
 wire F20Hz;

 reg [4:0] Cnt2;

 always @(negedge Clk)
	  Cnt1 <= Cnt1 + 1;

 assign F20Hz = Cnt1[1]; 
 
 always @(negedge F20Hz)
     if(Cnt2 == 24 )
	   Cnt2 <= 0;
     else
	   Cnt2 <= Cnt2 + 1;

 always @(Cnt2)
     if(Cnt2 == 21)
	   Catch <= 1;
	else 
	   Catch <= 0;

 always @(Cnt2)
     if(Cnt2 == 23)
	   Clear <= 1;
	else 
	   Clear <= 0;
	    
 always @(Cnt2)
     if(Cnt2 >= 20)
	   Latch <= 0;
	else 
	   Latch <= 1;

endmodule