tendiv.v

4位数字频率计的verilog HDL设计

module TenDiv(F10Div,Clock);

input Clock;
output F10Div;

reg [3:0] FOut;


always @(posedge Clock)
    if( FOut == 9 )
        FOut <= 0;
    else
        FOut <= FOut + 1 ;

assign F10Div = FOut[3] ;

endmodule