freq_m_1.v

4位数字频率计的verilog HDL设计

module freq_m_1( SegmentOut,DigitOut,Signal_in,Clock_in );	   //

input  Clock_in; 
input  Signal_in;

output [4:0] DigitOut;
output [6:0] SegmentOut; 

reg [4:0] DigitOut;
reg [6:0] SegmentOut; 

wire Latch;

wire [3:0] dig0,dig1,dig2,dig3,dig4;

wire [3:0] Digit_0,Digit_1,Digit_2,Digit_3,Digit_4;

wire [2:0] Sel;

reg [3:0] Data_out;



//产生闸门信号、锁存信号和计数器清0信号
DivStream Div1(Sel,Latch,Catch,Clear,Clock_in);


//将被测信号和闸门信号相与，得到计数信号
and AND1(sig,Latch,Signal_in);


//对输入被测信号进行计数，得到各位（十进制）的值
TenDiv4 Div2(dig0,Clear,sig);
TenDiv4 Div3(dig1,Clear,dig0[3]);
TenDiv4 Div4(dig2,Clear,dig1[3]);
TenDiv4 Div5(dig3,Clear,dig2[3]);
TenDiv4 Div6(dig4,Clear,dig3[3]);
//TenDiv4 Div7(dig5,Clear,dig4[3]);
//TenDiv4 Div8(dig6,Clear,dig5[3]);


//锁存器
DFF Dff0(Digit_0,dig0,Catch);
DFF Dff1(Digit_1,dig1,Catch);
DFF Dff2(Digit_2,dig2,Catch);
DFF Dff3(Digit_3,dig3,Catch);
DFF Dff4(Digit_4,dig4,Catch);
//DFF Dff5(Digit_5,dig5,Catch);
//DFF Dff6(Digit_6,dig6,Catch);


//选择器，用于显示	   
/*
always @( Sel or Digit_0 or Digit_1 or Digit_2 or Digit_3 or Digit_4 or Digit_5 or Digit_6)
   case ( Sel )
      3'b000 : begin Data_out = Digit_0; DigitOut = 7'b1111110; end
      3'b001 : begin Data_out = Digit_1; DigitOut = 7'b1111101; end
      3'b010 : begin Data_out = Digit_2; DigitOut = 7'b1111011; end
      3'b011 : begin Data_out = Digit_3; DigitOut = 7'b1110111; end
      3'b100 : begin Data_out = Digit_4; DigitOut = 7'b1101111; end
      3'b101 : begin Data_out = Digit_5; DigitOut = 7'b1011111; end
      3'b110 : begin Data_out = Digit_6; DigitOut = 7'b0111111; end
      3'b111 : begin Data_out = 0;       DigitOut = 7'b1111111; end
   endcase
*/


always @( Sel or Digit_0 or Digit_1 or Digit_2 or Digit_3 or Digit_4 )
   case ( Sel )
      3'b000 : Data_out <= Digit_0; 
      3'b001 : Data_out <= Digit_1; 
      3'b010 : Data_out <= Digit_2; 
      3'b011 : Data_out <= Digit_3; 
      3'b100 : Data_out <= Digit_4;  
     default : Data_out <= 0;      
   endcase


always @( Sel or Digit_0 or Digit_1 or Digit_2 or Digit_3 or Digit_4  )
   case ( Sel )
      3'b000 : DigitOut = 5'b11110; 
      3'b001 : DigitOut = 5'b11101; 
      3'b010 : DigitOut = 5'b11011;
      3'b011 : DigitOut = 5'b10111; 
      3'b100 : DigitOut = 5'b01111;  
      default: DigitOut = 5'b11111; 
   endcase


//译码器
always @(Data_out)
   case(Data_out)			// abcdefg
	 4'b0000 : SegmentOut <= 7'b0000001;
	 4'b0001 : SegmentOut <= 7'b1001111;
	 4'b0010 : SegmentOut <= 7'b0010010;
	 4'b0011 : SegmentOut <= 7'b0000110;
	 4'b0100 : SegmentOut <= 7'b1001100;
	 4'b0101 : SegmentOut <= 7'b0100100;
	 4'b0110 : SegmentOut <= 7'b0100000;
	 4'b0111 : SegmentOut <= 7'b0001111;
	 4'b1000 : SegmentOut <= 7'b0000000;
	 4'b1001 : SegmentOut <= 7'b0000100;
	 default : SegmentOut <= 7'bxxxxxxx;
   endcase


endmodule