mux_16x1_m.msg

16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！

@TM:1185694567
@N: FA174 :"":0:0:0:-1|The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1185694563
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1185694561
@N:  :"e:\fpfa\da_baseoncase\post\adder_mac.v":1:7:1:15|Synthesizing module adder_mac
@W: CS142 :"e:\fpfa\da_baseoncase\post\adder_mac.v":1:47:1:54|M
@TM:1185694563
@W: BN132 :"e:\fpfa\da_baseoncase\post\adder_mac.v":22:1:22:6|M
@TM:1185694561
@W: CL169 :"e:\fpfa\da_baseoncase\post\adder_mac.v":22:1:22:6|M
@N:  :"e:\fpfa\da_baseoncase\post\ctrl_all.v":2:7:2:14|Synthesizing module ctrl_all
@TM:1185694563
@N:  :"e:\fpfa\da_baseoncase\post\ctrl_all.v":8:0:8:5|M
@TM:1185694561
@N:  :"e:\fpfa\da_baseoncase\post\da_top.v":1:7:1:12|Synthesizing module DA_top
@N:  :"e:\fpfa\da_baseoncase\post\dacase8_1.v":1:7:1:15|Synthesizing module dacase8_1
@TM:1185694566
@N: FX214 :"e:\fpfa\da_baseoncase\post\dacase8_1.v":8:7:8:10|M
@TM:1185694561
@N:  :"e:\fpfa\da_baseoncase\post\dacase8_2.v":1:7:1:15|Synthesizing module dacase8_2
@TM:1185694566
@N: FX214 :"e:\fpfa\da_baseoncase\post\dacase8_2.v":8:7:8:10|M
@TM:1185694561
@N:  :"e:\fpfa\da_baseoncase\post\mux_16x1_m.v":4:7:4:14|Synthesizing module MUX_16X1
@TM:1185694566
@W: BN116 :"e:\fpfa\da_baseoncase\post\mux_16x1_m.v":14:0:14:5|M
@TM:1185694561
@N:  :"e:\fpfa\da_baseoncase\post\shift_ram.v":1:7:1:15|Synthesizing module shift_ram
@W: CL159 :"e:\fpfa\da_baseoncase\post\shift_ram.v":4:21:4:23|M