_primary.vhd

来自「16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity MUX_16X1 is
    port(
        MUXIN           : in     vl_logic_vector(15 downto 0);
        SEL             : in     vl_logic_vector(3 downto 0);
        MUXOUT          : out    vl_logic;
        CLK             : in     vl_logic
    );
end MUX_16X1;