_primary.vhd

来自「16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity DA_top is
    port(
        DAT_IN          : in     vl_logic_vector(15 downto 0);
        CLK             : in     vl_logic;
        CLK1_16         : in     vl_logic;
        RST             : in     vl_logic;
        RESULT          : out    vl_logic_vector(34 downto 0);
        RESULT_trun     : out    vl_logic_vector(18 downto 0);
        RDEN            : out    vl_logic
    );
end DA_top;