_primary.vhd

来自「16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity dacase8_2 is
    port(
        ADDR            : in     vl_logic_vector(7 downto 0);
        CLK             : in     vl_logic;
        Q               : out    vl_logic_vector(15 downto 0)
    );
end dacase8_2;