_primary.vhd

来自「16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity ctrl_all is
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        SHIFTEN         : in     vl_logic;
        SEL_mux         : out    vl_logic_vector(3 downto 0);
        SEL_add         : out    vl_logic_vector(3 downto 0)
    );
end ctrl_all;