_primary.vhd

来自「16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity adder_mac is
    port(
        A               : in     vl_logic_vector(15 downto 0);
        B               : in     vl_logic_vector(15 downto 0);
        CTRL_SIGN       : in     vl_logic_vector(3 downto 0);
        RST             : in     vl_logic;
        CLK             : in     vl_logic;
        \OUT\           : out    vl_logic_vector(34 downto 0);
        OUT_trun        : out    vl_logic_vector(18 downto 0);
        RDEN            : out    vl_logic
    );
end adder_mac;