mux_16x1_m.plg

来自「16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有」· PLG 代码 · 共 13 行

@P:  Part : EP1S10FC780-5
@P:  Worst Slack : 1.576
@P:  DA_top|CLK - Estimated Frequency : 213.9 MHz
@P:  DA_top|CLK - Requested Frequency : 160.0 MHz
@P:  DA_top|CLK - Estimated Period : 4.674
@P:  DA_top|CLK - Requested Period : 6.250
@P:  DA_top|CLK - Slack : 1.576
@P: DA_top Part : ep1s10fc780-5
@P: DA_top I/O ATOMs : 74
@P: DA_top Total LUTs: : 433 of 10570 ( 4%)
@P: DA_top Logic resources : 485 ATOMs of 10570 ( 4%)
@P: DA_top DSP Blocks : 0 (0 nine bit DSP elements)