_primary.vhd

来自「16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有」· VHDL 代码 · 共 27 行

library verilog;
use verilog.vl_types.all;
entity shift_ram is
    port(
        CLK             : in     vl_logic;
        SHIFTIN         : in     vl_logic_vector(15 downto 0);
        SHIFTEN         : in     vl_logic;
        RST             : in     vl_logic;
        TAP0            : out    vl_logic_vector(15 downto 0);
        TAP1            : out    vl_logic_vector(15 downto 0);
        TAP2            : out    vl_logic_vector(15 downto 0);
        TAP3            : out    vl_logic_vector(15 downto 0);
        TAP4            : out    vl_logic_vector(15 downto 0);
        TAP5            : out    vl_logic_vector(15 downto 0);
        TAP6            : out    vl_logic_vector(15 downto 0);
        TAP7            : out    vl_logic_vector(15 downto 0);
        TAP8            : out    vl_logic_vector(15 downto 0);
        TAP9            : out    vl_logic_vector(15 downto 0);
        TAP10           : out    vl_logic_vector(15 downto 0);
        TAP11           : out    vl_logic_vector(15 downto 0);
        TAP12           : out    vl_logic_vector(15 downto 0);
        TAP13           : out    vl_logic_vector(15 downto 0);
        TAP14           : out    vl_logic_vector(15 downto 0);
        TAP15           : out    vl_logic_vector(15 downto 0)
    );
end shift_ram;