_primary.vhd

16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！

library verilog;
use verilog.vl_types.all;
entity DA_top_tb is
    generic(
        data_file_name  : string  := "imp_in.txt";
        ENDDAT          : integer := 300;
        COEF_LENGTH     : integer := 16
    );
end DA_top_tb;