sap_1.v

SAP-1的硬體描述語言(使用Verilog語言)

module SAP_1(out,clk,clr);
output [7:0] out;
input clk,clr;
wire [7:0] bus;
wire [3:0] line1,line2;
wire [7:0] line3,line4;

	pc(bus[3:0],Cp,Ep,clk1,clr1_);
	mar(line1,Lm_,bus[3:0],clk1);
	rom(bus,line1,Ce_);
	IR(line2,bus[3:0],bus,Li_,Ei_,clk1,clr1);
	control(clk1,clr1,clk1_,clr1_,Cp,Ep,Lm_,Ce_,Li_,Ei_,La_,Ea,Su,Eu,Lb_,Lo_,clk,clr,line2);
	regA(bus,line3,bus,clk1,Ea,La_);
	addsub(bus,line3,line4,Su,Eu);
	regB(line4,bus,clk1,Lb_);
	regout(out,bus,clk1,Lo_);
	
endmodule