addsub.v

来自「SAP-1的硬體描述語言(使用Verilog語言)」· Verilog 代码 · 共 15 行

module addsub(S,A,B,Su,Eu);
output [7:0] S;
input [7:0] A,B;
input Su,Eu;
reg [7:0] S_temp;
wire [7:0] B_temp;

assign B_temp={Su, Su, Su, Su, Su, Su, Su, Su}^B;

always@(A or B_temp or Su)
	S_temp=A+B_temp+Su;

assign S = Eu ? S_temp : 8'bz;

endmodule