control.v

来自「SAP-1的硬體描述語言(使用Verilog語言)」· Verilog 代码 · 共 17 行

module control(clk1,clr1,clk1_,clr1_,Cp,Ep,Lm_,Ce_,Li_,Ei_,La_,Ea,Su,Eu,Lb_,Lo_,clk,clr,I);
output clk1,clr1,clk1_,clr1_,Cp,Ep,Lm_,Ce_,Li_,Ei_,La_,Ea,Su,Eu,Lb_,Lo_;
input clk,clr;
input [7:4] I;
wire [7:4] I;
wire lda, add, sub, out, hlt;
wire [6:1] t;

assign clk1=clk;
assign clr1=clr;
assign clk1_=~clk;
assign clr1_=~clr;
	op_decoder(lda,add,sub,out,hlt,I);
	ring_counter(t,clk1_,clr1);
	matrix(Cp,Ep,Lm_,Ce_,Li_,Ei_,La_,Ea,Su,Eu,Lb_,Lo_,t,lda,add,sub,out);
endmodule