regout.v

SAP-1的硬體描述語言(使用Verilog語言)

module regout(Q,D,clk,Lo_);
output [7:0] Q;
input [7:0] D;
input clk,Lo_;
reg [7:0] Q;

always@(posedge clk)
	if(Lo_==0) Q<=D;
endmodule