control_unit.v

SAP-1的硬體描述語言(使用Verilog語言)

module control_unit(CCp, EEp, _LLm, _CCe, _LL1, _EE1, _LLa, EEa, SSu, EEu, _LLb, _LLo, cclk, cclr, Icu);
output CCp, EEp, _LLm, _CCe, _LL1, _EE1, _LLa, EEa, SSu, EEu, _LLb, _LLo;
input cclk, cclr, Icu;
wire [7:4] Icu;
wire lda, add, sub, out, hlt;
wire [6:1] t;
op_decoder ode(lda, add, sub, out, hlt ,Icu);
ring_counter rc(t, cclk, cclr);
control_matrix(CCp, EEp, _LLm, _CCe, _LL1, _EE1, _LLa, EEa, SSu, EEu, _LLb, _LLo, t, lda, add, sub, out);
endmodule


module control_matrix(Cp, Ep, _Lm, _Ce, _L1, _E1, _La, Ea, Su, Eu, _Lb, _Lo, TT, LLDA, AADD, SSUB, OOUT);
output Cp, Ep, _Lm, _Ce, _L1, _E1, _La, Ea, Su, Eu, _Lb, _Lo;
input TT, LLDA, AADD, SSUB, OOUT;
wire [6:1] TT;
reg Cp, Ep, _Lm, _Ce, _L1, _E1, _La, Ea, Su, Eu, _Lb, _Lo;

always @(TT)
  case (TT)
      6'b000001: begin Cp=0; Ep=1; _Lm=~(TT[1]|LLDA&TT[4]|AADD&TT[4]|SSUB&TT[4]); _Ce=1; _L1=1; _E1=1; _La=1; Ea=0; Su=0; Eu=0; _Lb=1; _Lo=1; end
      6'b000010: begin Cp=1; Ep=0; _Lm=1; _Ce=1; _L1=1; _E1=1; _La=1; Ea=0; Su=0; Eu=0; _Lb=1; _Lo=1; end
      6'b000100: begin Cp=0; Ep=0; _Lm=1; _Ce=~(TT[3]|LLDA&TT[5]|AADD&TT[5]|SSUB&TT[5]); _L1=~TT[3]; _E1=1; _La=1; Ea=0; Su=0; Eu=0; _Lb=1; _Lo=1; end
      6'b001000: begin Cp=0; Ep=0; _Lm=~(TT[1]|LLDA&TT[4]|AADD&TT[4]|SSUB&TT[4]); _Ce=1; _L1=1; _E1=~(LLDA&TT[4]|AADD&TT[4]|SSUB&TT[4]); _La=1; Ea=OOUT&TT[4]; Su=0; Eu=0; _Lb=1;   _Lo=~(OOUT&TT[4]); end
      6'b010000: begin Cp=0; Ep=0; _Lm=1; _Ce=1; _L1=1; _E1=1; _La=~(LLDA&TT[5]|AADD&TT[6]|SSUB&TT[6]); Ea=0; Su=0; Eu=0; _Lb=~(AADD&TT[5]|SSUB&TT[5]); _Lo=1; end
      6'b100000: begin Cp=0; Ep=0; _Lm=1; _Ce=1; _L1=1; _E1=1; _La=~(LLDA&TT[5]|AADD&TT[6]|SSUB&TT[6]); Ea=0; Su=0; Eu=AADD&TT[6]|SSUB&TT[6]; _Lb=1; _Lo=1; end
  endcase
endmodule


module ring_counter(T, clk, clr);
output [6:1] T;
input clk, clr;
reg [6:1] T;

always @(negedge clk or posedge clr)
  if(clr==1)
    T <= 6'b000_001;
  else
    T <= {T[5:1], T[6]};

endmodule


module op_decoder(LDA, ADD, SUB, OUT, HLT, I);
output LDA, ADD, SUB, OUT, HLT;
input [7:4] I;
reg LDA, ADD, SUB, OUT, HLT;

always @(I)
  case(I)
    4'b0000: begin LDA=1; ADD=0; SUB=0; OUT=0; HLT=0; end
    4'b0001: begin LDA=0; ADD=1; SUB=0; OUT=0; HLT=0; end
    4'b0010: begin LDA=0; ADD=0; SUB=1; OUT=0; HLT=0; end
    4'b1110: begin LDA=0; ADD=0; SUB=0; OUT=1; HLT=0; end
    4'b1111: begin LDA=0; ADD=0; SUB=0; OUT=0; HLT=1; end
    default: begin LDA=0; ADD=0; SUB=0; OUT=0; HLT=0; end
  endcase
endmodule