cpu_test.v

这个文件中使用verilog hdl简单的利用基本运算实现了微型的cpu设计开发过程

`resetall
`include "defines.v"

module cpu_test; 

reg          rst_;
reg [12*8:1] testfile;
reg [23:0]   mnemonic;
reg [31:0]   test_number;

clockgen cgen   (                
                .clk   (clk   ),    
                .clk2  (clk2  ),
                .fetch (fetch ) 
                );

cpu     cpu1    (               
                .halt  (halt  ),
                .clk   (clk   ),     
                .clk2  (clk2  ),
                .fetch (fetch ),
                .rst_  (rst_  )
                );


  // Monitor Results

  initial
    $timeformat ( -9, 1, " ns", 12 );


  // Apply Stimulus

  initial  
    forever
      begin
        $display ( "" );
        $display ( "****************************************" );
        $display ( "THE FOLLOWING DEBUG TASKS ARE AVAILABLE:" );
        $display ( "1- The basic CPU diagnostic.            " );
        $display ( "2- The advanced CPU diagnostic.         " );
        $display ( "3- The Fibonacci program.               " );
        $display ( "****************************************" );
        $display ( "" );
        
        $display ( "Please Change test_number's value\n" );
        test_number = 1;
        //$stop; // wait for test number
        if ( test_number > 3 )
          begin
            $display ( "Test number %d is not between 1 and 3", test_number );
          end
        else
          begin
            case ( test_number )
              1: begin
                   $display ( "CPUtest1 - BASIC CPU DIAGNOSTIC PROGRAM \n" );
                   $display ( "THIS TEST SHOULD HALT WITH THE PC AT 17 hex\n" );
                 end
              2: begin
                   $display ( "CPUtest2 - ADVANCED CPU DIAGNOSTIC PROGRAM\n" );
                   $display ( "THIS TEST SHOULD HALT WITH THE PC AT 10 hex\n" );
                 end
              3: begin
                   $display ( "CPUtest3 - FIBONACCI NUMBERS to 144\n" );
                   $display ( "THIS TEST SHOULD HALT WITH THE PC AT 0C hex\n" );
                 end
            endcase
            testfile = { "CPUtest", 8'h30+test_number[7:0], ".dat" };
            $readmemb ( testfile, cpu1.mem1.memory );
            @ ( negedge clk ) rst_ = 0;
            @ ( negedge clk ) rst_ = 1;
            $display("     TIME       PC    INSTR    OP   ADR   DATA\n");
            $display("  ----------    --    -----    --   ---   ----\n");
            while ( !halt )
              @( posedge clk )
              if ( cpu1.load_ir )
                begin
                  #(`PERIOD/4)
                  case ( cpu1.opcode )
                    3'h0   : mnemonic = "HLT";
                    3'h1   : mnemonic = "SKZ";
                    3'h2   : mnemonic = "ADD";
                    3'h3   : mnemonic = "AND";
                    3'h4   : mnemonic = "XOR";
                    3'h5   : mnemonic = "LDA";
                    3'h6   : mnemonic = "STO";
                    3'h7   : mnemonic = "JMP";
                    default: mnemonic = "???";
                  endcase
                  $display ( "%t    %h    %s      %h    %h     %h",
                    $time,cpu1.pc_addr,mnemonic,cpu1.opcode,
                    cpu1.addr,cpu1.data );
                  if ( test_number == 3 && mnemonic == "JMP" )
                   $display ( "Next Fibonacci number is %d",
                     cpu1.mem1.memory[5'h1B] );
                end
            if ( test_number == 1 && cpu1.pc_addr != 5'h18
              || test_number == 2 && cpu1.pc_addr != 5'h11
              || test_number == 3 && cpu1.pc_addr != 5'h0D )
              begin
                $display ( "CPU TEST FAILED" );
                $finish;
              end
            $display ( "\nCPU TEST PASSED" );
            $finish;
          end
      end

endmodule