combfilter.v

adc verilog 用verilog编写的sigma-delta adc例子 应用在计量类adc产品

`include "NINTER.V"
`include "NDIFF.V"

//--Difinition of Comb filter-------------------------------
`define	TAP	1000     //Over Sample Rate  
`define	N	10         //Over Sample Rate bits log2(TAP)
`define	RLN	22       //Comb Filter Integator Length  K+log2(TAP)+2
`define	SUMLEN	16   //Comb Filter effective number
//----------------------------------------------------------
module COMBFILTER(DCMSYN,ADCSUM,DIN,SPLCLK,ADCCON_RST0,ADCCON_MODE,
	TSTEN,TSTIN);
//----------------------------------------------------------
//DCMSYN:       ADC Decimation synchrous clock
//ADCSUM[15:0]: ADC converted date,16-bit signed integer
//DIN:          Bitsmodulated by sigma-delta modulator
//SPCLK:        Over sample clock synchrous to DIN
//ADCCON_RST0:  Control reg RST0: 0 resets ADC;1 enable normal work
//ADCCON_MODE:  Control reg mode:0 select normal mode;1 select fast mode;
//TSTEN:        Test mode enable
//TSTIN:        To replace DIN during test period
//----------------------------------------------------------
output		DCMSYN;
output	[15:0]	ADCSUM;
input		DIN;
input		SPLCLK;
input		ADCCON_RST0,ADCCON_MODE;
input		TSTEN,TSTIN;

reg		DCMSYN;
reg	[15:0]	ADCSUM;
wire		sdmin;
reg	[9:0]	counter;
wire	[21:0]	sum_in,sum1,sum2;
wire	[16:0]	sum_w;
wire	[16:0]	diff1,diff2;

//- decimation counter
always @(posedge SPLCLK or negedge ADCCON_RST0)
	if(!ADCCON_RST0)begin
		counter[9:0]		<= 10'h000;
		ADCSUM[15:0]		<= 16'h0000;
		end
	else if((counter==999) | ((ADCCON_MODE==1) & (counter==10'h03f)))
		counter[9:0]		<= 10'h000;
	else begin
		counter[9:0]		<= counter[9:0]+1'b1;
		if(DCMSYN)
			ADCSUM[15:0]	<= diff2[16:1];
		end
always @(negedge SPLCLK or negedge ADCCON_RST0)
	if(!ADCCON_RST0)
		DCMSYN	<= 1'b0;
	else if(counter[9:0]==0)
		DCMSYN	<= 1'b1;
	else
		DCMSYN	<= 1'b0;

//- Multiplexer for input
assign	sdmin	= TSTEN ? TSTIN : DIN;
assign	sum_in	= sdmin ?   1   :  -1;


//- combfilter and decimator
assign	sum_w	= sum2[21:5];
NINTER	m1(.sum(sum1),.in(sum_in),.clk(SPLCLK),.rst0(ADCCON_RST0));
NINTER	m2(.sum(sum2),.in(sum1)  ,.clk(SPLCLK),.rst0(ADCCON_RST0));
NDIFF	m3(.diff(diff1),.in(sum_w),.ckd(DCMSYN),.clk(SPLCLK),.rst0(ADCCON_RST0));
NDIFF	m4(.diff(diff2),.in(diff1),.ckd(DCMSYN),.clk(SPLCLK),.rst0(ADCCON_RST0));


endmodule