readmem.v

来自「adc verilog 用verilog编写的sigma-delta adc例」· Verilog 代码 · 共 34 行

//read memory data
//If en=1,the initial counter automatic increases and data stream output with
//  the posedge clk
`define MAX_SIZE 1000010

module memory(data,clk,cs);
output		data;
input		clk;
input		cs;
    

reg		data;
reg		mem[1:`MAX_SIZE];
integer	counter;


//read memory file
initial begin
	data	=0;
	counter	=0;
	$readmemb("modulate.rom",mem);
	end


always @(posedge clk)begin
	if(counter>`MAX_SIZE)
		$finish;    
	if(cs)begin
		counter=counter+1;
		data=mem[counter];
		end
	end

endmodule