combfilter_wrap.vhd

来自「adc verilog 用verilog编写的sigma-delta adc例」· VHDL 代码 · 共 59 行

----------------------------------------------------------------
-- Module combfilter VHDL Wrapper
--
-- Generated by The MathWorks wrapverilog tcl command
--
-- Generated on: 2007-04-26 22:38:43
--
----------------------------------------------------------------
LIBRARY IEEE;
  USE IEEE.std_logic_1164.all;

ENTITY combfilter_wrap IS

    port(
        DCMSYN          : out   std_logic;
        ADCSUM          : out   std_logic_vector(15 downto 0);
        DIN             : in    std_logic;
        SPLCLK          : in    std_logic;
        ADCCON_RST0     : in    std_logic;
        ADCCON_MODE     : in    std_logic;
        TSTEN           : in    std_logic;
        TSTIN           : in    std_logic
    );

END combfilter_wrap;

ARCHITECTURE rtl OF combfilter_wrap IS

component COMBFILTER 
    port(
        DCMSYN          : out   std_logic;
        ADCSUM          : out   std_logic_vector(15 downto 0);
        DIN             : in    std_logic;
        SPLCLK          : in    std_logic;
        ADCCON_RST0     : in    std_logic;
        ADCCON_MODE     : in    std_logic;
        TSTEN           : in    std_logic;
        TSTIN           : in    std_logic
    );
end component;

FOR ALL : combfilter
  USE ENTITY work.combfilter(ignored);

BEGIN
  u_combfilter: combfilter
    PORT MAP (
      DCMSYN  => DCMSYN ,
      ADCSUM  => ADCSUM ,
      DIN  => DIN ,
      SPLCLK  => SPLCLK ,
      ADCCON_RST0  => ADCCON_RST0 ,
      ADCCON_MODE  => ADCCON_MODE ,
      TSTEN  => TSTEN ,
      TSTIN  => TSTIN 
    );

END rtl;