combfilter_tb.v

adc verilog 用verilog编写的sigma-delta adc例子 应用在计量类adc产品

`include "ninter.v"
`include "ndiff.v"
`include "combfilter.v"
`include "readmem.v"
module COMBFILTER_tb  ; 
 
  reg 		ADCCON_MODE   ; 
  reg    	ADCCON_RST0   ; 
  reg    	SPLCLK   ; 
  wire [15:0]  	ADCSUM   ; 
  reg    	TSTIN   ; 
  reg    	TSTEN   ; 
  wire    	DCMSYN   ; 
  wire    	DIN   ; 

  
  integer   	fileid,cont;
  
  memory   SIM(.data(DIN),.clk(SPLCLK),.cs(ADCCON_RST0));
  
  COMBFILTER  
   DUT  ( 
       .ADCCON_MODE (ADCCON_MODE ) ,
      .ADCCON_RST0 (ADCCON_RST0 ) ,
      .SPLCLK (SPLCLK ) ,
      .ADCSUM (ADCSUM ) ,
      .TSTIN (TSTIN ) ,
      .TSTEN (TSTEN ) ,
      .DCMSYN (DCMSYN ) ,
      .DIN (DIN ) ); 


initial begin
	fileid=$fopen("m1.dat");
	if(!fileid)begin
		$display("Error\n");
		$finish;
		end
       
    ADCCON_MODE        =1'b0;
    ADCCON_RST0        =1'b0;
    TSTEN        =1'b0;
    TSTIN        =1'b0;
//    DIN        =1'b0;
    SPLCLK        =1'b0;
    cont   =0;
    
    #200
        ADCCON_RST0=1'b1;

    #1000000000   $fclose(fileid);
    $finish;
            end

always @(negedge DCMSYN)begin
	cont=cont+1;
	$fdisplay(fileid,"%d  %d",cont,ADCSUM[15:0]);
	end

always #50
	SPLCLK=~SPLCLK;

always #50000000 $stop;
/*
always begin
    #4000 DIN=1'b0;
    #6000 DIN=1'b1;
   end
*/
endmodule