_primary.vhd

两条5级的并行流水线

library verilog;
use verilog.vl_types.all;
entity IRLoader is
    port(
        ID1             : out    vl_logic_vector(16 downto 0);
        IR1             : out    vl_logic_vector(31 downto 0);
        ID2             : out    vl_logic_vector(16 downto 0);
        IR2             : out    vl_logic_vector(31 downto 0);
        PC2             : out    vl_logic_vector(31 downto 0);
        Adr             : out    vl_logic_vector(31 downto 0);
        RamD            : in     vl_logic_vector(63 downto 0);
        NewPc           : in     vl_logic_vector(31 downto 0);
        RA              : in     vl_logic;
        LdPc            : in     vl_logic;
        Read1           : in     vl_logic;
        Read2           : in     vl_logic;
        clr             : in     vl_logic;
        clk             : in     vl_logic
    );
end IRLoader;