bin_bcd_3.v

基于Verilog-HDL的硬件电路的实现 9.2 具有LCD显示单元的可编程单脉冲发生器 9.2.1 LCD显示单元的工作原理 9.2.2 显示逻辑设计的思路与流程 9.

						
module BIN_BCD_3 (CLK, RESET, A, BW, BQ, BB, BS, BG);		
    input CLK;
    input RESET;
    input  [16:0]A;        
    output [3:0]BW, BQ, BB, BS, BG;        	
    reg    [3:0]BW, BQ, BB, BS, BG;         	
						
    integer CNT;
    reg  [19:0]BCD;
    reg  [16:0]BIN_INPUT;
						
    function [3:0]CORRECT ;		
	input [3:0]DECADE;
	begin				
	   CORRECT = (DECADE >= 5) ? (DECADE+3) : (DECADE);
        end
    endfunction		
						
    always @ (posedge CLK or negedge RESET)
     begin
       if (!RESET)                   		
	  begin             	    
	    CNT = 18;
	    BCD = 20'b0000_0000_0000_0000_0000;
            BIN_INPUT=17'b0_0000_0000_0000_0000;
            BW=4'b0000;
            BQ=4'b0000;
            BB=4'b0000;
            BS=4'b0000;
            BG=4'b0000;
          end
	else  if (CNT == 18) 
             begin   
		BIN_INPUT=A;  
                CNT=CNT-1;              
             end
	else  if (CNT==0)
             begin
              BW=BCD[19:16];
              BQ=BCD[15:12];
              BB=BCD[11:8];
              BS=BCD[7:4];
              BG=BCD[3:0];
             end
        else
	     begin
                BCD[3:0] = CORRECT(BCD[3:0]);
		BCD[7:4] = CORRECT(BCD[7:4]);
		BCD[11:8] = CORRECT(BCD[11:8]);
		BCD[15:12] = CORRECT(BCD[15:12]);	
		BCD[19:16] = CORRECT(BCD[19:16]);	
	  
                CNT = CNT - 1;
		BCD = (BCD << 1);
		BCD[0] = BIN_INPUT[16];
                BIN_INPUT = BIN_INPUT << 1;
	     end
     end				   
endmodule