bin_bcd_2_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.2 具有LCD显示单元的可编」· Verilog 代码 · 共 28 行

`timescale    1ps/1ps
module  BIN_BCD_2_TEST;
    reg     CLK;
    reg     [16:0] A; 
    wire    [3:0] BW, BQ, BB, BS, BG;
    

    BIN_BCD_2  BIN_BCD_2 (CLK, A, BW, BQ, BB, BS, BG);

    always #10 CLK=~CLK;

    initial
      begin
       CLK=0; A=17'd0;   //0
       #50  A=17'd28;    //28
       #50  A=17'd735;   //735
       #50  A=17'd6984;   //6984
       #50  A=17'd57623;   //57623
       #50  A=17'd99999;   //99999
       #50  $finish; 
      end
endmodule