bin_bcd_1_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.2 具有LCD显示单元的可编」· Verilog 代码 · 共 27 行

`timescale    1ps/1ps
module  BIN_BCD_1_TEST;
    reg     [16:0] A;
    reg     CLK;
    wire    [3:0] BW, BQ, BB, BS, BG;
    

    BIN_BCD_1  BIN_BCD_1 (CLK, A, BW, BQ, BB, BS, BG);

    always #10 CLK=~CLK;

    initial
      begin
       CLK=0; A=17'b0_0000_0000_0000_1100;  //12
       #50  A=17'b0_0000_0010_0000_1000;    //520
       #50  A=17'b0_0000_0011_1111_1111;     //1023
       #50  A=17'b0_1111_1111_1111_1111;     //65535
       #50  A=17'b1_1000_0110_1001_1111;     //99999
       #50  $finish; 
      end
endmodule