bin_bcd_4.v

来自「基于Verilog-HDL的硬件电路的实现 9.2 具有LCD显示单元的可编」· Verilog 代码 · 共 48 行

					
module BIN_BCD_4 (CLK, A, BW, BQ, BB, BS, BG);		
    input CLK;
    input  [16:0]A;        
    output [3:0]BW, BQ, BB, BS, BG;        	
    reg    [3:0]BW, BQ, BB, BS, BG;      
  					
    integer I;
    reg  [19:0]TEMP;
    reg  [16:0]C;
						
    					
    always @ (posedge CLK)
     begin
       C=A;
       TEMP=0;

       for (I=1; I<17; I=I+1)
           begin
           {TEMP, C}={TEMP[18:0], C, 1'b0};
           if (TEMP[3:0]>4'b0100)
              begin
                TEMP[3:0]=TEMP[3:0]+3;
              end 
           if (TEMP[7:4]>4'b0100)
              begin
                TEMP[7:4]=TEMP[7:4]+3;
              end 
           if (TEMP[11:8]>4'b0100)
              begin
                TEMP[11:8]=TEMP[11:8]+3;
              end 
           if (TEMP[15:12]>4'b0100)
              begin
                TEMP[15:12]=TEMP[15:12]+3;
              end 
           if (TEMP[19:16]>4'b0100)
              begin
                TEMP[19:16]=TEMP[19:16]+3;
              end 
           {BW, BQ, BB,  BS, BG}={TEMP[18:0], A[0]};
           end
     end
  
endmodule