bin_bcd_3_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.2 具有LCD显示单元的可编」· Verilog 代码 · 共 24 行

`timescale 1ps / 1ps
						
module BIN_BCD_3_TEST;		
    reg CLK;
    reg RESET;
    reg  [16:0]A;        
    wire [3:0]BW, BQ, BB, BS, BG;          	
						
    BIN_BCD_3  BIN_BCD_3  (CLK, RESET, A, BW, BQ, BB, BS, BG);	

    always #1 CLK=~CLK;
						
    initial
      begin
        CLK=0; A=17'd246; RESET=1;
        #2  RESET=0;
        #2  RESET=1;
        #45 A=17'd35789; 
        #2  RESET=0;
        #2  RESET=1;
        #45 $finish;
      end
endmodule