bin_bcd_1.v

来自「基于Verilog-HDL的硬件电路的实现 9.2 具有LCD显示单元的可编」· Verilog 代码 · 共 30 行

module  BIN_BCD_1  (CLK, A, BW, BQ, BB, BS, BG);
    input     CLK;
    input     [16:0] A;          // 输入00-99999
    output    [3:0] BW, BQ, BB, BS, BG; 
    reg       [3:0] BW, BQ, BB, BS, BG; 
                                // BW表示万位，BQ表示千位，BB表示百位数，BS表示十位数，BG表示个位数
    reg       [13:0] TMP_1;
    reg       [9:0] TMP_2;
    reg       [6:0] TMP_3;

    
   always @ (posedge CLK)
      begin
         BW=A/10000;
         TMP_1=A%10000;
         BQ=TMP_1/1000;
         TMP_2=TMP_1%1000;
         BB=TMP_2/100;
         TMP_3=TMP_2%100;
         BS=TMP_3/10;
         BG=TMP_3%10;
      end
endmodule