bin_bcd_4_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.2 具有LCD显示单元的可编」· Verilog 代码 · 共 22 行

`timescale 1ps / 1ps
						
module BIN_BCD_4_TEST;		
    reg CLK;
    reg  [16:0]A;        
    wire [3:0]BW, BQ, BB, BS, BG;          	
						
    BIN_BCD_4  BIN_BCD_4 (CLK, A, BW, BQ, BB, BS, BG);
	
    always #1 CLK=~CLK;
						
    initial
      begin
        CLK=0; A=17'd0;
        #5 A=17'd246; 
        #5 A=17'd5789; 
        #5 A=17'd46032; 
        #5 A=17'd99999; 
        #5 $finish;
      end
endmodule