counter.vo

用verilog实现单片机计数器 用verilog实现单片机计数器

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version"

// DATE "10/15/2006 22:27:46"

// 
// Device: Altera EP1C12Q240C8 Package PQFP240
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module counter (
	po,
	clock,
	rst,
	MO,
	M1,
	led4,
	led3);
output 	po;
input 	clock;
input 	rst;
input 	MO;
input 	M1;
output 	led4;
output 	led3;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("counter_v.sdo");
// synopsys translate_on

wire \inst5|state.s_run ;
wire \inst1|state.s_run ;
wire \clock~combout ;
wire \MO~combout ;
wire \M1~combout ;
wire \rst~combout ;
wire \inst2|comb~8 ;
wire \inst2|comb~9 ;
wire \inst13|Add0~284 ;
wire \inst13|TOUT0[0]~833 ;
wire \inst13|Add0~285 ;
wire \inst13|Add0~285COUT1_287 ;
wire \inst13|Add0~282 ;
wire \inst13|Add0~283 ;
wire \inst13|Add0~283COUT1_288 ;
wire \inst13|Add0~280 ;
wire \inst13|Add0~281 ;
wire \inst13|Add0~278 ;
wire \inst13|Add0~279 ;
wire \inst13|Add0~279COUT1_289 ;
wire \inst13|Add0~276 ;
wire \inst13|Add0~277 ;
wire \inst13|Add0~277COUT1_290 ;
wire \inst13|Add0~274 ;
wire \inst13|Add0~275 ;
wire \inst13|Add0~275COUT1_291 ;
wire \inst13|Add0~272 ;
wire \inst13|Add0~273 ;
wire \inst13|Add0~273COUT1_292 ;
wire \inst13|Add0~270 ;
wire \inst13|Add0~271 ;
wire \inst13|Add0~268 ;
wire \inst13|Add0~269 ;
wire \inst13|Add0~269COUT1_293 ;
wire \inst13|Add0~266 ;
wire \inst13|Add0~267 ;
wire \inst13|Add0~267COUT1_294 ;
wire \inst13|Add0~264 ;
wire \inst13|Add0~265 ;
wire \inst13|Add0~265COUT1_295 ;
wire \inst13|Add0~262 ;
wire \inst13|Add0~263 ;
wire \inst13|Add0~263COUT1_296 ;
wire \inst13|Add0~260 ;
wire \inst13|Add0~261 ;
wire \inst13|Add0~258 ;
wire \inst13|Add0~259 ;
wire \inst13|Add0~259COUT1_297 ;
wire \inst13|Add0~256 ;
wire \inst13|Add0~257 ;
wire \inst13|Add0~257COUT1_298 ;
wire \inst13|Add0~254 ;
wire \inst13|Add0~255 ;
wire \inst13|Add0~255COUT1_299 ;
wire \inst13|Add0~252 ;
wire \inst12|Add0~148 ;
wire \inst12|TF1[0]~64 ;
wire \inst12|Add0~149 ;
wire \inst12|Add0~149COUT1_151 ;
wire \inst12|Add0~146 ;
wire \inst12|Add0~147 ;
wire \inst12|Add0~147COUT1_152 ;
wire \inst12|Add0~144 ;
wire \inst12|Add0~145 ;
wire \inst12|Add0~145COUT1_153 ;
wire \inst12|Add0~142 ;
wire \inst12|Add0~143 ;
wire \inst12|Add0~143COUT1 ;
wire \inst12|Add0~140 ;
wire \inst12|Add0~141 ;
wire \inst12|Add0~138 ;
wire \inst12|Add0~139 ;
wire \inst12|Add0~139COUT1_154 ;
wire \inst12|Add0~136 ;
wire \inst12|Add0~137 ;
wire \inst12|Add0~137COUT1_155 ;
wire \inst12|Add0~134 ;
wire \inst12|Add0~135 ;
wire \inst12|Add0~135COUT1_156 ;
wire \inst12|Add0~132 ;
wire [0:0] \inst12|TF1 ;
wire [7:0] \inst12|TL ;
wire [0:0] \inst13|TF0 ;
wire [15:0] \inst13|TOUT0 ;
wire [0:0] \inst2|ENABLE0 ;
wire [0:0] \inst2|ENABLE1 ;
wire [0:0] \inst2|LED3 ;
wire [0:0] \inst2|LED4 ;
wire [0:0] \inst2|TF_ALL ;
wire [7:0] \inst2|TH ;
wire [0:0] \inst|P0 ;


// atom is at PIN_28
cyclone_io \clock~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clock~combout ),
	.regout(),
	.padio(clock));
// synopsys translate_off
defparam \clock~I .input_async_reset = "none";
defparam \clock~I .input_power_up = "low";
defparam \clock~I .input_register_mode = "none";
defparam \clock~I .input_sync_reset = "none";
defparam \clock~I .oe_async_reset = "none";
defparam \clock~I .oe_power_up = "low";
defparam \clock~I .oe_register_mode = "none";
defparam \clock~I .oe_sync_reset = "none";
defparam \clock~I .operation_mode = "input";
defparam \clock~I .output_async_reset = "none";
defparam \clock~I .output_power_up = "low";
defparam \clock~I .output_register_mode = "none";
defparam \clock~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_140
cyclone_io \MO~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\MO~combout ),
	.regout(),
	.padio(MO));
// synopsys translate_off
defparam \MO~I .input_async_reset = "none";
defparam \MO~I .input_power_up = "low";
defparam \MO~I .input_register_mode = "none";
defparam \MO~I .input_sync_reset = "none";
defparam \MO~I .oe_async_reset = "none";
defparam \MO~I .oe_power_up = "low";
defparam \MO~I .oe_register_mode = "none";
defparam \MO~I .oe_sync_reset = "none";
defparam \MO~I .operation_mode = "input";
defparam \MO~I .output_async_reset = "none";
defparam \MO~I .output_power_up = "low";
defparam \MO~I .output_register_mode = "none";
defparam \MO~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_144
cyclone_io \M1~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\M1~combout ),
	.regout(),
	.padio(M1));
// synopsys translate_off
defparam \M1~I .input_async_reset = "none";
defparam \M1~I .input_power_up = "low";
defparam \M1~I .input_register_mode = "none";
defparam \M1~I .input_sync_reset = "none";
defparam \M1~I .oe_async_reset = "none";
defparam \M1~I .oe_power_up = "low";
defparam \M1~I .oe_register_mode = "none";
defparam \M1~I .oe_sync_reset = "none";
defparam \M1~I .operation_mode = "input";
defparam \M1~I .output_async_reset = "none";
defparam \M1~I .output_power_up = "low";
defparam \M1~I .output_register_mode = "none";
defparam \M1~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_17
cyclone_io \rst~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rst~combout ),
	.regout(),
	.padio(rst));
// synopsys translate_off
defparam \rst~I .input_async_reset = "none";
defparam \rst~I .input_power_up = "low";
defparam \rst~I .input_register_mode = "none";
defparam \rst~I .input_sync_reset = "none";
defparam \rst~I .oe_async_reset = "none";
defparam \rst~I .oe_power_up = "low";
defparam \rst~I .oe_register_mode = "none";
defparam \rst~I .oe_sync_reset = "none";
defparam \rst~I .operation_mode = "input";
defparam \rst~I .output_async_reset = "none";
defparam \rst~I .output_power_up = "low";
defparam \rst~I .output_register_mode = "none";
defparam \rst~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X18_Y16_N2
cyclone_lcell \inst2|comb~8_I (
// Equation(s):
// \inst2|comb~8  = !\M1~combout  & \MO~combout  # !\rst~combout 

	.clk(gnd),
	.dataa(\M1~combout ),
	.datab(\MO~combout ),
	.datac(\rst~combout ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst2|comb~8 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst2|comb~8_I .lut_mask = "4F4F";
defparam \inst2|comb~8_I .operation_mode = "normal";
defparam \inst2|comb~8_I .output_mode = "comb_only";
defparam \inst2|comb~8_I .register_cascade_mode = "off";
defparam \inst2|comb~8_I .sum_lutc_input = "datac";
defparam \inst2|comb~8_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X18_Y16_N1
cyclone_lcell \inst2|ENABLE0[0]~I (
// Equation(s):
// \inst2|ENABLE0 [0] = !\inst2|comb~8  & (\inst2|ENABLE0 [0] # !\MO~combout )

	.clk(gnd),
	.dataa(vcc),
	.datab(\MO~combout ),
	.datac(\inst2|comb~8 ),
	.datad(\inst2|ENABLE0 [0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst2|ENABLE0 [0]),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst2|ENABLE0[0]~I .lut_mask = "0F03";
defparam \inst2|ENABLE0[0]~I .operation_mode = "normal";
defparam \inst2|ENABLE0[0]~I .output_mode = "comb_only";
defparam \inst2|ENABLE0[0]~I .register_cascade_mode = "off";
defparam \inst2|ENABLE0[0]~I .sum_lutc_input = "datac";
defparam \inst2|ENABLE0[0]~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X18_Y16_N5
cyclone_lcell \inst2|comb~9_I (
// Equation(s):
// \inst2|comb~9  = !\rst~combout  # !\MO~combout 

	.clk(gnd),
	.dataa(vcc),
	.datab(\MO~combout ),
	.datac(\rst~combout ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst2|comb~9 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst2|comb~9_I .lut_mask = "3F3F";
defparam \inst2|comb~9_I .operation_mode = "normal";
defparam \inst2|comb~9_I .output_mode = "comb_only";
defparam \inst2|comb~9_I .register_cascade_mode = "off";
defparam \inst2|comb~9_I .sum_lutc_input = "datac";
defparam \inst2|comb~9_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X18_Y16_N6
cyclone_lcell \inst2|ENABLE1[0]~I (
// Equation(s):
// \inst2|ENABLE1 [0] = !\inst2|comb~9  & (\inst2|ENABLE1 [0] # !\M1~combout )

	.clk(gnd),
	.dataa(\M1~combout ),
	.datab(\inst2|comb~9 ),
	.datac(vcc),
	.datad(\inst2|ENABLE1 [0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst2|ENABLE1 [0]),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst2|ENABLE1[0]~I .lut_mask = "3311";
defparam \inst2|ENABLE1[0]~I .operation_mode = "normal";
defparam \inst2|ENABLE1[0]~I .output_mode = "comb_only";
defparam \inst2|ENABLE1[0]~I .register_cascade_mode = "off";
defparam \inst2|ENABLE1[0]~I .sum_lutc_input = "datac";
defparam \inst2|ENABLE1[0]~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X17_Y16_N2
cyclone_lcell \inst13|Add0~284_I (
// Equation(s):
// \inst13|Add0~284  = !\inst13|TOUT0 [0]
// \inst13|Add0~285  = CARRY(\inst13|TOUT0 [0])
// \inst13|Add0~285COUT1_287  = CARRY(\inst13|TOUT0 [0])

	.clk(gnd),
	.dataa(vcc),
	.datab(\inst13|TOUT0 [0]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst13|Add0~284 ),
	.regout(),
	.cout(),
	.cout0(\inst13|Add0~285 ),
	.cout1(\inst13|Add0~285COUT1_287 ));
// synopsys translate_off
defparam \inst13|Add0~284_I .lut_mask = "33CC";