_primary.vhd

来自「用verilog实现单片机计数器 用verilog实现单片机计数器」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity data0 is
    port(
        RST             : in     vl_logic_vector(0 downto 0);
        CLOCK           : in     vl_logic_vector(0 downto 0);
        ADD             : in     vl_logic_vector(0 downto 0);
        THIN            : in     vl_logic_vector(7 downto 0);
        TLIN            : in     vl_logic_vector(7 downto 0);
        TOUT0           : out    vl_logic_vector(15 downto 0);
        LOAD            : in     vl_logic_vector(0 downto 0);
        TF              : out    vl_logic_vector(0 downto 0);
        LED2            : out    vl_logic_vector(0 downto 0);
        TCLOCK          : out    vl_logic_vector(0 downto 0)
    );
end data0;