_primary.vhd

来自「用verilog实现单片机计数器 用verilog实现单片机计数器」· VHDL 代码 · 共 22 行

library verilog;
use verilog.vl_types.all;
entity count_all is
    port(
        CLOCK           : in     vl_logic_vector(0 downto 0);
        M0              : in     vl_logic_vector(0 downto 0);
        M1              : in     vl_logic_vector(0 downto 0);
        RST             : in     vl_logic_vector(0 downto 0);
        ENABLE0         : out    vl_logic_vector(0 downto 0);
        ENABLE1         : out    vl_logic_vector(0 downto 0);
        LED4            : out    vl_logic_vector(0 downto 0);
        LED3            : out    vl_logic_vector(0 downto 0);
        TF_ALL          : out    vl_logic_vector(0 downto 0);
        TF0             : in     vl_logic_vector(0 downto 0);
        TF1             : in     vl_logic_vector(0 downto 0);
        TH              : out    vl_logic_vector(7 downto 0);
        TL              : out    vl_logic_vector(7 downto 0);
        THIN            : in     vl_logic_vector(7 downto 0);
        TLIN            : in     vl_logic_vector(7 downto 0)
    );
end count_all;