counter.plg

来自「用verilog实现单片机计数器 用verilog实现单片机计数器」· PLG 代码 · 共 13 行

@P:  Part : EP1C12QC240-7
@P:  Worst Slack : -0.505
@P:  counter|clock - Estimated Frequency : 297.2 MHz
@P:  counter|clock - Requested Frequency : 349.7 MHz
@P:  counter|clock - Estimated Period : 3.364
@P:  counter|clock - Requested Period : 2.860
@P:  counter|clock - Slack : -0.505
@P: counter Part : ep1c12qc240-7
@P: counter I/O ATOMs : 7
@P: counter Total LUTs: : 45 of 12060 ( 0%)
@P: counter Logic resources : 45 ATOMs of 12060 ( 0%)
@P:  CPU Time : 0h:00m:00s