_primary.vhd

来自「用verilog实现单片机计数器 用verilog实现单片机计数器」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity counter is
    port(
        MO              : in     vl_logic;
        rst             : in     vl_logic;
        clock           : in     vl_logic;
        M1              : in     vl_logic;
        po              : out    vl_logic;
        led4            : out    vl_logic;
        led3            : out    vl_logic
    );
end counter;