_primary.vhd

来自「用verilog实现单片机计数器 用verilog实现单片机计数器」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity data0 is
    port(
        RST             : in     vl_logic_vector(0 downto 0);
        CLOCK           : in     vl_logic_vector(0 downto 0);
        ADD             : in     vl_logic_vector(0 downto 0);
        TH              : in     vl_logic_vector(7 downto 0);
        TL              : in     vl_logic_vector(7 downto 0);
        TF0             : out    vl_logic_vector(0 downto 0)
    );
end data0;