_primary.vhd

来自「用verilog实现单片机计数器 用verilog实现单片机计数器」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity control0 is
    generic(
        s_idle          : integer := 1;
        s_run           : integer := 2
    );
    port(
        ENABLE0         : in     vl_logic_vector(0 downto 0);
        TR              : in     vl_logic_vector(0 downto 0);
        RST             : in     vl_logic_vector(0 downto 0);
        CLOCK           : in     vl_logic_vector(0 downto 0);
        ADD             : out    vl_logic_vector(0 downto 0)
    );
end control0;