counter.fit.qmsg

用verilog实现单片机计数器 用verilog实现单片机计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 17 09:56:18 2006 " "Info: Processing started: Tue Oct 17 09:56:18 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off counter -c counter " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off counter -c counter" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "counter EP1C12Q240C7 " "Info: Selected device EP1C12Q240C7 for design \"counter\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C7 " "Info: Device EP1C6Q240C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240I7 " "Info: Device EP1C6Q240I7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240I7 " "Info: Device EP1C12Q240I7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clock Global clock in PIN 28 " "Info: Automatically promoted signal \"clock\" to use Global clock in PIN 28" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst Global clock " "Info: Automatically promoted some destinations of signal \"rst\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "count_all:b2v_inst2\|LED4_0__Z " "Info: Destination \"count_all:b2v_inst2\|LED4_0__Z\" may be non-global or may not use global clock" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1009 16 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "count_all:b2v_inst2\|LED3_0__Z " "Info: Destination \"count_all:b2v_inst2\|LED3_0__Z\" may be non-global or may not use global clock" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1008 16 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "test:b2v_inst\|P0_0__Z " "Info: Destination \"test:b2v_inst\|P0_0__Z\" may be non-global or may not use global clock" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 29 14 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data1:b2v_inst12\|TF1_0__Z " "Info: Destination \"data1:b2v_inst12\|TF1_0__Z\" may be non-global or may not use global clock" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 118 15 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data0:b2v_inst13\|TF0_0__Z " "Info: Destination \"data0:b2v_inst13\|TF0_0__Z\" may be non-global or may not use global clock" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 453 15 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "count_all:b2v_inst2\|ENABLE118_x_cZ " "Info: Destination \"count_all:b2v_inst2\|ENABLE118_x_cZ\" may be non-global or may not use global clock" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1034 19 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "count_all:b2v_inst2\|un1_M1_1_x_cZ " "Info: Destination \"count_all:b2v_inst2\|un1_M1_1_x_cZ\" may be non-global or may not use global clock" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1033 18 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "count_all:b2v_inst2\|un1_RST_1_x_cZ " "Info: Destination \"count_all:b2v_inst2\|un1_RST_1_x_cZ\" may be non-global or may not use global clock" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1035 19 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data1:b2v_inst12\|TF1_1_sqmuxa_x_cZ " "Info: Destination \"data1:b2v_inst12\|TF1_1_sqmuxa_x_cZ\" may be non-global or may not use global clock" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 133 22 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data0:b2v_inst13\|TF0_1_sqmuxa_x_cZ " "Info: Destination \"data0:b2v_inst13\|TF0_1_sqmuxa_x_cZ\" may be non-global or may not use global clock" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 470 22 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1281 12 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst " "Info: Pin \"rst\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1281 12 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}