counter.map.qmsg

用verilog实现单片机计数器 用verilog实现单片机计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 17 09:56:13 2006 " "Info: Processing started: Tue Oct 17 09:56:13 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counter -c counter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off counter -c counter" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vqm 7 7 " "Info: Found 7 design units, including 7 entities, in source file counter.vqm" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 22 12 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 control1_1_2 " "Info: Found entity 2: control1_1_2" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 64 20 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 data1 " "Info: Found entity 3: data1" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 108 13 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 data0 " "Info: Found entity 4: data0" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 441 13 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 count_all " "Info: Found entity 5: count_all" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 990 17 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 control0_1_2 " "Info: Found entity 6: control0_1_2" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1227 20 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 counter " "Info: Found entity 7: counter" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1271 15 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "counter " "Info: Elaborating entity \"counter\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "test test:b2v_inst " "Info: Elaborating entity \"test\" for hierarchy \"test:b2v_inst\"" {  } { { "counter.vqm" "b2v_inst" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1419 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control1_1_2 control1_1_2:b2v_inst1 " "Info: Elaborating entity \"control1_1_2\" for hierarchy \"control1_1_2:b2v_inst1\"" {  } { { "counter.vqm" "b2v_inst1" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1426 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data1 data1:b2v_inst12 " "Info: Elaborating entity \"data1\" for hierarchy \"data1:b2v_inst12\"" {  } { { "counter.vqm" "b2v_inst12" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1435 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data0 data0:b2v_inst13 " "Info: Elaborating entity \"data0\" for hierarchy \"data0:b2v_inst13\"" {  } { { "counter.vqm" "b2v_inst13" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1445 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count_all count_all:b2v_inst2 " "Info: Elaborating entity \"count_all\" for hierarchy \"count_all:b2v_inst2\"" {  } { { "counter.vqm" "b2v_inst2" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1461 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus60/libraries/megafunctions/lpm_latch.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/lpm_latch.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_latch " "Info: Found entity 1: lpm_latch" {  } { { "lpm_latch.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_latch.tdf" 34 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_latch count_all:b2v_inst2\|lpm_latch:ENABLE0_1_0_ " "Info: Elaborating entity \"lpm_latch\" for hierarchy \"count_all:b2v_inst2\|lpm_latch:ENABLE0_1_0_\"" {  } { { "counter.vqm" "ENABLE0_1_0_" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1062 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "count_all:b2v_inst2\|lpm_latch:ENABLE0_1_0_ " "Info: Elaborated megafunction instantiation \"count_all:b2v_inst2\|lpm_latch:ENABLE0_1_0_\"" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1062 3 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_latch count_all:b2v_inst2\|lpm_latch:ENABLE1_0_ " "Info: Elaborating entity \"lpm_latch\" for hierarchy \"count_all:b2v_inst2\|lpm_latch:ENABLE1_0_\"" {  } { { "counter.vqm" "ENABLE1_0_" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1074 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "count_all:b2v_inst2\|lpm_latch:ENABLE1_0_ " "Info: Elaborated megafunction instantiation \"count_all:b2v_inst2\|lpm_latch:ENABLE1_0_\"" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1074 3 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control0_1_2 control0_1_2:b2v_inst5 " "Info: Elaborating entity \"control0_1_2\" for hierarchy \"control0_1_2:b2v_inst5\"" {  } { { "counter.vqm" "b2v_inst5" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1468 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "55 " "Info: Implemented 55 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "48 " "Info: Implemented 48 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 17 09:56:15 2006 " "Info: Processing ended: Tue Oct 17 09:56:15 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}