counter.hier_info

用verilog实现单片机计数器 用verilog实现单片机计数器

|counter
MO => MO_in.PADIO
rst => rst_in.PADIO
clock => clock_in.PADIO
M1 => M1_in.PADIO
po <= po_out.PADIO
led4 <= led4_out.PADIO
led3 <= led3_out.PADIO


|counter|test:b2v_inst
TF_ALL_0 => P0_0__Z.DATAB
P0_0 <= P0_0__Z.REGOUT
rst_c => P0_0__Z.DATAA
clock_c => P0_0__Z.CLK


|counter|control1_1_2:b2v_inst1
SYNTHESIZED_WIRE_1_0 => state_1__Z.DATAD
state_0 <= state_1__Z.REGOUT
rst_c => rst_c_i.IN0
clock_c => state_1__Z.CLK


|counter|data1:b2v_inst12
SYNTHESIZED_WIRE_1_0 => un1_ADD_x_cZ.DATAA
SYNTHESIZED_WIRE_1_0 => TF1_1_a_0_.DATAA
state_0 => TF1_0__Z.DATAC
state_0 => un1_ADD_x_cZ.DATAC
TF1_0 <= TF1_0__Z.REGOUT
TOUT0_6_x_0 => TL_0__Z.DATAC
TOUT0_6_x_0 => TL_1__Z.DATAC
TOUT0_6_x_0 => TL_3__Z.DATAC
rst_c => TF1_0__Z.DATAA
rst_c => TF1_1_sqmuxa_x_cZ.DATAA
rst_c => un1_ADD_x_cZ.DATAB
clock_c => TL_0__Z.CLK
clock_c => TL_1__Z.CLK
clock_c => TL_2__Z.CLK
clock_c => TL_3__Z.CLK
clock_c => TL_4__Z.CLK
clock_c => TL_5__Z.CLK
clock_c => TL_6__Z.CLK
clock_c => TL_7__Z.CLK
clock_c => TF1_0__Z.CLK


|counter|data0:b2v_inst13
ENABLE0_1_0 => un1_ADD_x_cZ.DATAA
ENABLE0_1_0 => TF0_1_a_0_.DATAA
TH_0 => TOUT0_6_x_11_.DATAB
state_0 => TF0_0__Z.DATAC
state_0 => un1_ADD_x_cZ.DATAC
TF0_0 <= TF0_0__Z.REGOUT
TOUT0_6_x_0 <= TOUT0_6_x_11_.COMBOUT
rst_c => TF0_0__Z.DATAA
rst_c => TOUT0_6_x_11_.DATAA
rst_c => TF0_1_sqmuxa_x_cZ.DATAA
rst_c => un1_ADD_x_cZ.DATAB
clock_c => TOUT0_0__Z.CLK
clock_c => TOUT0_1__Z.CLK
clock_c => TOUT0_2__Z.CLK
clock_c => TOUT0_3__Z.CLK
clock_c => TOUT0_4__Z.CLK
clock_c => TOUT0_5__Z.CLK
clock_c => TOUT0_6__Z.CLK
clock_c => TOUT0_7__Z.CLK
clock_c => TOUT0_8__Z.CLK
clock_c => TOUT0_9__Z.CLK
clock_c => TOUT0_10__Z.CLK
clock_c => TOUT0_11__Z.CLK
clock_c => TOUT0_12__Z.CLK
clock_c => TOUT0_13__Z.CLK
clock_c => TOUT0_14__Z.CLK
clock_c => TOUT0_15__Z.CLK
clock_c => TF0_0__Z.CLK


|counter|count_all:b2v_inst2
TF0_0 => TF_ALL_0__Z.DATAD
TF1_0 => TF_ALL_0__Z.DATAC
TF_ALL_0 <= TF_ALL_0__Z.REGOUT
LED3_0 <= LED3_0__Z.REGOUT
LED4_0 <= LED4_0__Z.REGOUT
TH_0 <= TH_3__Z.REGOUT
SYNTHESIZED_WIRE_1_0 <= lpm_latch:ENABLE1_0_.q
ENABLE0_1_0 <= lpm_latch:ENABLE0_1_0_.q
M1_c => un1_M1_1_x_cZ.DATAB
MO_c => ENABLE118_x_cZ.DATAB
MO_c => un1_RST_1_x_cZ.DATAB
rst_c => LED4_0__Z.DATAA
rst_c => LED3_0__Z.DATAA
rst_c => ENABLE118_x_cZ.DATAA
rst_c => un1_M1_1_x_cZ.DATAA
rst_c => un1_RST_1_x_cZ.DATAA
clock_c => TH_3__Z.CLK
clock_c => LED4_0__Z.CLK
clock_c => LED3_0__Z.CLK
clock_c => TF_ALL_0__Z.CLK
I_59_x_i => lpm_latch:ENABLE1_0_.aset


|counter|count_all:b2v_inst2|lpm_latch:ENABLE0_1_0_
data[0] => latches[0].DATAIN
gate => latches[0].LATCH_ENABLE
aconst => ~NO_FANOUT~
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE


|counter|count_all:b2v_inst2|lpm_latch:ENABLE1_0_
data[0] => latches[0].DATAIN
gate => latches[0].LATCH_ENABLE
aconst => ~NO_FANOUT~
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE


|counter|control0_1_2:b2v_inst5
ENABLE0_1_0 => state_1__Z.DATAA
state_0 <= state_1__Z.REGOUT
rst_c => rst_c_i.IN0
clock_c => state_1__Z.CLK