counter.tan.qmsg

用verilog实现单片机计数器 用verilog实现单片机计数器

{ "Info" "ITDB_TH_RESULT" "data1:b2v_inst12\|TF1_0 rst clock -3.762 ns register " "Info: th for register \"data1:b2v_inst12\|TF1_0\" (data pin = \"rst\", clock pin = \"clock\") is -3.762 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.869 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clock 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.629 ns) 2.869 ns data1:b2v_inst12\|TF1_0 2 REG LC_X5_Y18_N6 4 " "Info: 2: + IC(0.941 ns) + CELL(0.629 ns) = 2.869 ns; Loc. = LC_X5_Y18_N6; Fanout = 4; REG Node = 'data1:b2v_inst12\|TF1_0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.570 ns" { clock data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 118 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 67.20 % ) " "Info: Total cell delay = 1.928 ns ( 67.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.941 ns ( 32.80 % ) " "Info: Total interconnect delay = 0.941 ns ( 32.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data1:b2v_inst12|TF1_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.013 ns + " "Info: + Micro hold delay of destination is 0.013 ns" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 118 15 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.644 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.644 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns rst 1 PIN PIN_17 15 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 15; PIN Node = 'rst'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1281 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.922 ns) + CELL(0.423 ns) 6.644 ns data1:b2v_inst12\|TF1_0 2 REG LC_X5_Y18_N6 4 " "Info: 2: + IC(4.922 ns) + CELL(0.423 ns) = 6.644 ns; Loc. = LC_X5_Y18_N6; Fanout = 4; REG Node = 'data1:b2v_inst12\|TF1_0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.345 ns" { rst data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 118 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.722 ns ( 25.92 % ) " "Info: Total cell delay = 1.722 ns ( 25.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.922 ns ( 74.08 % ) " "Info: Total interconnect delay = 4.922 ns ( 74.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.644 ns" { rst data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.644 ns" { rst rst~out0 data1:b2v_inst12|TF1_0 } { 0.000ns 0.000ns 4.922ns } { 0.000ns 1.299ns 0.423ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data1:b2v_inst12|TF1_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.644 ns" { rst data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.644 ns" { rst rst~out0 data1:b2v_inst12|TF1_0 } { 0.000ns 0.000ns 4.922ns } { 0.000ns 1.299ns 0.423ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Minimum Pulse Width Requirement (High) 33 " "Warning: Can't achieve timing requirement Minimum Pulse Width Requirement (High) along 33 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Minimum Pulse Width Requirement (Low) 33 " "Warning: Can't achieve timing requirement Minimum Pulse Width Requirement (Low) along 33 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}
{ "Info" "ITDB_FULL_MIN_PULSE_RESULT" "clock test:b2v_inst\|P0_0 -0.133 ns " "Info: Minimum pulse width minimum slack time is -0.133 ns between clock \"clock\" and destination register \"test:b2v_inst\|P0_0\"" { { "Info" "ITDB_ACTUAL_PULSE_RESULT" "non-inverted clock high 1.429 ns + " "Info: + non-inverted clock path from clock \"clock\" to destination has high pulse width of 1.429 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 2.859 ns 0.000 ns non-inverted 50 " "Info: Clock period of Source clock \"clock\" is 2.859 ns with non-inverted offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { clock } {  } {  } } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "%5!c! %1!s! clock path from clock \"%2!s!\" to destination has %3!s! pulse width of %4!s!" 0 0} { "Info" "ITDB_REQUIRED_PULSE_RESULT" "test:b2v_inst\|P0_0 high 1.562 ns - " "Info: - Register \"test:b2v_inst\|P0_0\" has a high minimum pulse width requirement of 1.562 ns" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { test:b2v_inst|P0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { test:b2v_inst|P0_0 } {  } {  } } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 29 14 0 } }  } 0 0 "%4!c! Register \"%1!s!\" has a %2!s! minimum pulse width requirement of %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { test:b2v_inst|P0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { clock } {  } {  } } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { test:b2v_inst|P0_0 } {  } {  } } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 29 14 0 } }  } 0 0 "Minimum pulse width minimum slack time is %3!s! between clock \"%1!s!\" and destination register \"%2!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_PULSE_RESULT" "clock test:b2v_inst\|P0_0 -0.132 ns " "Info: Minimum pulse width minimum slack time is -0.132 ns between clock \"clock\" and destination register \"test:b2v_inst\|P0_0\"" { { "Info" "ITDB_ACTUAL_PULSE_RESULT" "non-inverted clock low 1.430 ns + " "Info: + non-inverted clock path from clock \"clock\" to destination has low pulse width of 1.430 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 2.859 ns 0.000 ns non-inverted 50 " "Info: Clock period of Source clock \"clock\" is 2.859 ns with non-inverted offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { clock } {  } {  } } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "%5!c! %1!s! clock path from clock \"%2!s!\" to destination has %3!s! pulse width of %4!s!" 0 0} { "Info" "ITDB_REQUIRED_PULSE_RESULT" "test:b2v_inst\|P0_0 low 1.562 ns - " "Info: - Register \"test:b2v_inst\|P0_0\" has a low minimum pulse width requirement of 1.562 ns" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { test:b2v_inst|P0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { test:b2v_inst|P0_0 } {  } {  } } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 29 14 0 } }  } 0 0 "%4!c! Register \"%1!s!\" has a %2!s! minimum pulse width requirement of %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { test:b2v_inst|P0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { clock } {  } {  } } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { test:b2v_inst|P0_0 } {  } {  } } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 29 14 0 } }  } 0 0 "Minimum pulse width minimum slack time is %3!s! between clock \"%1!s!\" and destination register \"%2!s!\"" 0 0}