counter.tan.qmsg

用verilog实现单片机计数器 用verilog实现单片机计数器

{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'clock' 32 " "Warning: Can't achieve timing requirement Clock Setup: 'clock' along 32 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}
{ "Warning" "WTDB_CLOCK_REQ_RESTRICTED" "clock 3.124 ns " "Warning: Clock period specified in clock requirement for clock \"clock\" must be greater than or equal to the I/O edge rate limit of 3.124 ns in the currently selected device" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "Clock period specified in clock requirement for clock \"%1!s!\" must be greater than or equal to the I/O edge rate limit of %2!s! in the currently selected device" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock register data1:b2v_inst12\|TF1_0 register count_all:b2v_inst2\|TF_ALL_0 972 ps " "Info: Minimum slack time is 972 ps for clock \"clock\" between source register \"data1:b2v_inst12\|TF1_0\" and destination register \"count_all:b2v_inst2\|TF_ALL_0\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.787 ns + Shortest register register " "Info: + Shortest register to register delay is 0.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data1:b2v_inst12\|TF1_0 1 REG LC_X5_Y18_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y18_N6; Fanout = 4; REG Node = 'data1:b2v_inst12\|TF1_0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 118 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(0.273 ns) 0.787 ns count_all:b2v_inst2\|TF_ALL_0 2 REG LC_X5_Y18_N8 1 " "Info: 2: + IC(0.514 ns) + CELL(0.273 ns) = 0.787 ns; Loc. = LC_X5_Y18_N8; Fanout = 1; REG Node = 'count_all:b2v_inst2\|TF_ALL_0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.787 ns" { data1:b2v_inst12|TF1_0 count_all:b2v_inst2|TF_ALL_0 } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1007 18 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.273 ns ( 34.69 % ) " "Info: Total cell delay = 0.273 ns ( 34.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.514 ns ( 65.31 % ) " "Info: Total interconnect delay = 0.514 ns ( 65.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.787 ns" { data1:b2v_inst12|TF1_0 count_all:b2v_inst2|TF_ALL_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.787 ns" { data1:b2v_inst12|TF1_0 count_all:b2v_inst2|TF_ALL_0 } { 0.000ns 0.514ns } { 0.000ns 0.273ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.185 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.185 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 2.859 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 2.859 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 2.859 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 2.859 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.869 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clock 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.629 ns) 2.869 ns count_all:b2v_inst2\|TF_ALL_0 2 REG LC_X5_Y18_N8 1 " "Info: 2: + IC(0.941 ns) + CELL(0.629 ns) = 2.869 ns; Loc. = LC_X5_Y18_N8; Fanout = 1; REG Node = 'count_all:b2v_inst2\|TF_ALL_0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.570 ns" { clock count_all:b2v_inst2|TF_ALL_0 } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1007 18 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 67.20 % ) " "Info: Total cell delay = 1.928 ns ( 67.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.941 ns ( 32.80 % ) " "Info: Total interconnect delay = 0.941 ns ( 32.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock count_all:b2v_inst2|TF_ALL_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 count_all:b2v_inst2|TF_ALL_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.869 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to source register is 2.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clock 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.629 ns) 2.869 ns data1:b2v_inst12\|TF1_0 2 REG LC_X5_Y18_N6 4 " "Info: 2: + IC(0.941 ns) + CELL(0.629 ns) = 2.869 ns; Loc. = LC_X5_Y18_N6; Fanout = 4; REG Node = 'data1:b2v_inst12\|TF1_0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.570 ns" { clock data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 118 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 67.20 % ) " "Info: Total cell delay = 1.928 ns ( 67.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.941 ns ( 32.80 % ) " "Info: Total interconnect delay = 0.941 ns ( 32.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data1:b2v_inst12|TF1_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock count_all:b2v_inst2|TF_ALL_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 count_all:b2v_inst2|TF_ALL_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data1:b2v_inst12|TF1_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns - " "Info: - Micro clock to output delay of source is 0.198 ns" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 118 15 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.013 ns + " "Info: + Micro hold delay of destination is 0.013 ns" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1007 18 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock count_all:b2v_inst2|TF_ALL_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 count_all:b2v_inst2|TF_ALL_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data1:b2v_inst12|TF1_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.787 ns" { data1:b2v_inst12|TF1_0 count_all:b2v_inst2|TF_ALL_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.787 ns" { data1:b2v_inst12|TF1_0 count_all:b2v_inst2|TF_ALL_0 } { 0.000ns 0.514ns } { 0.000ns 0.273ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock count_all:b2v_inst2|TF_ALL_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 count_all:b2v_inst2|TF_ALL_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data1:b2v_inst12|TF1_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data1:b2v_inst12|TF1_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "data0:b2v_inst13\|TOUT0\[7\] rst clock 5.826 ns register " "Info: tsu for register \"data0:b2v_inst13\|TOUT0\[7\]\" (data pin = \"rst\", clock pin = \"clock\") is 5.826 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.662 ns + Longest pin register " "Info: + Longest pin to register delay is 8.662 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns rst 1 PIN PIN_17 15 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 15; PIN Node = 'rst'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1281 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.922 ns) + CELL(0.258 ns) 6.479 ns data0:b2v_inst13\|TF0_1_sqmuxa_x 2 COMB LC_X5_Y18_N7 17 " "Info: 2: + IC(4.922 ns) + CELL(0.258 ns) = 6.479 ns; Loc. = LC_X5_Y18_N7; Fanout = 17; COMB Node = 'data0:b2v_inst13\|TF0_1_sqmuxa_x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.180 ns" { rst data0:b2v_inst13|TF0_1_sqmuxa_x } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 470 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.099 ns) + CELL(1.084 ns) 8.662 ns data0:b2v_inst13\|TOUT0\[7\] 3 REG LC_X4_Y19_N9 2 " "Info: 3: + IC(1.099 ns) + CELL(1.084 ns) = 8.662 ns; Loc. = LC_X4_Y19_N9; Fanout = 2; REG Node = 'data0:b2v_inst13\|TOUT0\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.183 ns" { data0:b2v_inst13|TF0_1_sqmuxa_x data0:b2v_inst13|TOUT0[7] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 466 19 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.641 ns ( 30.49 % ) " "Info: Total cell delay = 2.641 ns ( 30.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.021 ns ( 69.51 % ) " "Info: Total interconnect delay = 6.021 ns ( 69.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.662 ns" { rst data0:b2v_inst13|TF0_1_sqmuxa_x data0:b2v_inst13|TOUT0[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.662 ns" { rst rst~out0 data0:b2v_inst13|TF0_1_sqmuxa_x data0:b2v_inst13|TOUT0[7] } { 0.000ns 0.000ns 4.922ns 1.099ns } { 0.000ns 1.299ns 0.258ns 1.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 466 19 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.869 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clock 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.629 ns) 2.869 ns data0:b2v_inst13\|TOUT0\[7\] 2 REG LC_X4_Y19_N9 2 " "Info: 2: + IC(0.941 ns) + CELL(0.629 ns) = 2.869 ns; Loc. = LC_X4_Y19_N9; Fanout = 2; REG Node = 'data0:b2v_inst13\|TOUT0\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.570 ns" { clock data0:b2v_inst13|TOUT0[7] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 466 19 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 67.20 % ) " "Info: Total cell delay = 1.928 ns ( 67.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.941 ns ( 32.80 % ) " "Info: Total interconnect delay = 0.941 ns ( 32.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data0:b2v_inst13|TOUT0[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data0:b2v_inst13|TOUT0[7] } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.662 ns" { rst data0:b2v_inst13|TF0_1_sqmuxa_x data0:b2v_inst13|TOUT0[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.662 ns" { rst rst~out0 data0:b2v_inst13|TF0_1_sqmuxa_x data0:b2v_inst13|TOUT0[7] } { 0.000ns 0.000ns 4.922ns 1.099ns } { 0.000ns 1.299ns 0.258ns 1.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data0:b2v_inst13|TOUT0[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data0:b2v_inst13|TOUT0[7] } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock po test:b2v_inst\|P0_0 8.302 ns register " "Info: tco from clock \"clock\" to destination pin \"po\" through register \"test:b2v_inst\|P0_0\" is 8.302 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.869 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clock 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.629 ns) 2.869 ns test:b2v_inst\|P0_0 2 REG LC_X5_Y17_N3 2 " "Info: 2: + IC(0.941 ns) + CELL(0.629 ns) = 2.869 ns; Loc. = LC_X5_Y17_N3; Fanout = 2; REG Node = 'test:b2v_inst\|P0_0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.570 ns" { clock test:b2v_inst|P0_0 } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 29 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 67.20 % ) " "Info: Total cell delay = 1.928 ns ( 67.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.941 ns ( 32.80 % ) " "Info: Total interconnect delay = 0.941 ns ( 32.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock test:b2v_inst|P0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 test:b2v_inst|P0_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 29 14 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.235 ns + Longest register pin " "Info: + Longest register to pin delay is 5.235 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns test:b2v_inst\|P0_0 1 REG LC_X5_Y17_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y17_N3; Fanout = 2; REG Node = 'test:b2v_inst\|P0_0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { test:b2v_inst|P0_0 } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 29 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.370 ns) + CELL(1.865 ns) 5.235 ns po 2 PIN PIN_88 0 " "Info: 2: + IC(3.370 ns) + CELL(1.865 ns) = 5.235 ns; Loc. = PIN_88; Fanout = 0; PIN Node = 'po'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.235 ns" { test:b2v_inst|P0_0 po } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1284 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.865 ns ( 35.63 % ) " "Info: Total cell delay = 1.865 ns ( 35.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.370 ns ( 64.37 % ) " "Info: Total interconnect delay = 3.370 ns ( 64.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.235 ns" { test:b2v_inst|P0_0 po } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.235 ns" { test:b2v_inst|P0_0 po } { 0.000ns 3.370ns } { 0.000ns 1.865ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock test:b2v_inst|P0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 test:b2v_inst|P0_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.235 ns" { test:b2v_inst|P0_0 po } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.235 ns" { test:b2v_inst|P0_0 po } { 0.000ns 3.370ns } { 0.000ns 1.865ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}