counter.tan.qmsg

用verilog实现单片机计数器 用verilog实现单片机计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 17 09:56:32 2006 " "Info: Processing started: Tue Oct 17 09:56:32 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off counter -c counter --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off counter -c counter --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "count_all:b2v_inst2\|lpm_latch:ENABLE0_1_0_\|latches\[0\] " "Warning: Node \"count_all:b2v_inst2\|lpm_latch:ENABLE0_1_0_\|latches\[0\]\" is a latch" {  } { { "lpm_latch.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_latch.tdf" 49 10 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "count_all:b2v_inst2\|lpm_latch:ENABLE1_0_\|latches\[0\] " "Warning: Node \"count_all:b2v_inst2\|lpm_latch:ENABLE1_0_\|latches\[0\]\" is a latch" {  } { { "lpm_latch.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_latch.tdf" 49 10 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clock register data0:b2v_inst13\|TOUT0\[0\] register data0:b2v_inst13\|TF0_0 -742 ps " "Info: Slack time is -742 ps for clock \"clock\" between source register \"data0:b2v_inst13\|TOUT0\[0\]\" and destination register \"data0:b2v_inst13\|TF0_0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "277.7 MHz 3.601 ns " "Info: Fmax is 277.7 MHz (period= 3.601 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.628 ns + Largest register register " "Info: + Largest register to register requirement is 2.628 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "2.859 ns + " "Info: + Setup relationship between source and destination is 2.859 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 2.859 ns " "Info: + Latch edge is 2.859 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 2.859 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 2.859 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 2.859 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 2.859 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.869 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clock 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.629 ns) 2.869 ns data0:b2v_inst13\|TF0_0 2 REG LC_X5_Y18_N3 4 " "Info: 2: + IC(0.941 ns) + CELL(0.629 ns) = 2.869 ns; Loc. = LC_X5_Y18_N3; Fanout = 4; REG Node = 'data0:b2v_inst13\|TF0_0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.570 ns" { clock data0:b2v_inst13|TF0_0 } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 453 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 67.20 % ) " "Info: Total cell delay = 1.928 ns ( 67.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.941 ns ( 32.80 % ) " "Info: Total interconnect delay = 0.941 ns ( 32.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data0:b2v_inst13|TF0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data0:b2v_inst13|TF0_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.869 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clock 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 1282 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.629 ns) 2.869 ns data0:b2v_inst13\|TOUT0\[0\] 2 REG LC_X4_Y19_N2 3 " "Info: 2: + IC(0.941 ns) + CELL(0.629 ns) = 2.869 ns; Loc. = LC_X4_Y19_N2; Fanout = 3; REG Node = 'data0:b2v_inst13\|TOUT0\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.570 ns" { clock data0:b2v_inst13|TOUT0[0] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 466 19 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 67.20 % ) " "Info: Total cell delay = 1.928 ns ( 67.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.941 ns ( 32.80 % ) " "Info: Total interconnect delay = 0.941 ns ( 32.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data0:b2v_inst13|TOUT0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data0:b2v_inst13|TOUT0[0] } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data0:b2v_inst13|TF0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data0:b2v_inst13|TF0_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data0:b2v_inst13|TOUT0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data0:b2v_inst13|TOUT0[0] } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns - " "Info: - Micro clock to output delay of source is 0.198 ns" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 466 19 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns - " "Info: - Micro setup delay of destination is 0.033 ns" {  } { { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 453 15 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data0:b2v_inst13|TF0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data0:b2v_inst13|TF0_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data0:b2v_inst13|TOUT0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data0:b2v_inst13|TOUT0[0] } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.370 ns - Longest register register " "Info: - Longest register to register delay is 3.370 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data0:b2v_inst13\|TOUT0\[0\] 1 REG LC_X4_Y19_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y19_N2; Fanout = 3; REG Node = 'data0:b2v_inst13\|TOUT0\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data0:b2v_inst13|TOUT0[0] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 466 19 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.499 ns) 0.971 ns data0:b2v_inst13\|TOUT0_cout\[0\] 2 COMB LC_X4_Y19_N2 2 " "Info: 2: + IC(0.472 ns) + CELL(0.499 ns) = 0.971 ns; Loc. = LC_X4_Y19_N2; Fanout = 2; COMB Node = 'data0:b2v_inst13\|TOUT0_cout\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.971 ns" { data0:b2v_inst13|TOUT0[0] data0:b2v_inst13|TOUT0_cout[0] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 465 24 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.069 ns) 1.040 ns data0:b2v_inst13\|TOUT0_cout\[1\] 3 COMB LC_X4_Y19_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.069 ns) = 1.040 ns; Loc. = LC_X4_Y19_N3; Fanout = 2; COMB Node = 'data0:b2v_inst13\|TOUT0_cout\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.069 ns" { data0:b2v_inst13|TOUT0_cout[0] data0:b2v_inst13|TOUT0_cout[1] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 465 24 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.157 ns) 1.197 ns data0:b2v_inst13\|TOUT0_cout\[2\] 4 COMB LC_X4_Y19_N4 6 " "Info: 4: + IC(0.000 ns) + CELL(0.157 ns) = 1.197 ns; Loc. = LC_X4_Y19_N4; Fanout = 6; COMB Node = 'data0:b2v_inst13\|TOUT0_cout\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.157 ns" { data0:b2v_inst13|TOUT0_cout[1] data0:b2v_inst13|TOUT0_cout[2] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 465 24 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.184 ns) 1.381 ns data0:b2v_inst13\|TOUT0_cout\[7\] 5 COMB LC_X4_Y19_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.184 ns) = 1.381 ns; Loc. = LC_X4_Y19_N9; Fanout = 6; COMB Node = 'data0:b2v_inst13\|TOUT0_cout\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.184 ns" { data0:b2v_inst13|TOUT0_cout[2] data0:b2v_inst13|TOUT0_cout[7] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 465 24 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.120 ns) 1.501 ns data0:b2v_inst13\|TOUT0_cout\[12\] 6 COMB LC_X4_Y18_N4 4 " "Info: 6: + IC(0.000 ns) + CELL(0.120 ns) = 1.501 ns; Loc. = LC_X4_Y18_N4; Fanout = 4; COMB Node = 'data0:b2v_inst13\|TOUT0_cout\[12\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.120 ns" { data0:b2v_inst13|TOUT0_cout[7] data0:b2v_inst13|TOUT0_cout[12] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 465 24 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.549 ns) 2.050 ns data0:b2v_inst13\|TOUT0_term_combout\[15\] 7 COMB LC_X4_Y18_N8 1 " "Info: 7: + IC(0.000 ns) + CELL(0.549 ns) = 2.050 ns; Loc. = LC_X4_Y18_N8; Fanout = 1; COMB Node = 'data0:b2v_inst13\|TOUT0_term_combout\[15\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.549 ns" { data0:b2v_inst13|TOUT0_cout[12] data0:b2v_inst13|TOUT0_term_combout[15] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 464 33 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.628 ns) + CELL(0.258 ns) 2.936 ns data0:b2v_inst13\|TF0_1_a\[0\] 8 COMB LC_X5_Y18_N2 1 " "Info: 8: + IC(0.628 ns) + CELL(0.258 ns) = 2.936 ns; Loc. = LC_X5_Y18_N2; Fanout = 1; COMB Node = 'data0:b2v_inst13\|TF0_1_a\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.886 ns" { data0:b2v_inst13|TOUT0_term_combout[15] data0:b2v_inst13|TF0_1_a[0] } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 467 20 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.161 ns) + CELL(0.273 ns) 3.370 ns data0:b2v_inst13\|TF0_0 9 REG LC_X5_Y18_N3 4 " "Info: 9: + IC(0.161 ns) + CELL(0.273 ns) = 3.370 ns; Loc. = LC_X5_Y18_N3; Fanout = 4; REG Node = 'data0:b2v_inst13\|TF0_0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.434 ns" { data0:b2v_inst13|TF0_1_a[0] data0:b2v_inst13|TF0_0 } "NODE_NAME" } } { "counter.vqm" "" { Text "D:/Quartus/MCU-counter/syn/rev_1/counter.vqm" 453 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.109 ns ( 62.58 % ) " "Info: Total cell delay = 2.109 ns ( 62.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.261 ns ( 37.42 % ) " "Info: Total interconnect delay = 1.261 ns ( 37.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.370 ns" { data0:b2v_inst13|TOUT0[0] data0:b2v_inst13|TOUT0_cout[0] data0:b2v_inst13|TOUT0_cout[1] data0:b2v_inst13|TOUT0_cout[2] data0:b2v_inst13|TOUT0_cout[7] data0:b2v_inst13|TOUT0_cout[12] data0:b2v_inst13|TOUT0_term_combout[15] data0:b2v_inst13|TF0_1_a[0] data0:b2v_inst13|TF0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.370 ns" { data0:b2v_inst13|TOUT0[0] data0:b2v_inst13|TOUT0_cout[0] data0:b2v_inst13|TOUT0_cout[1] data0:b2v_inst13|TOUT0_cout[2] data0:b2v_inst13|TOUT0_cout[7] data0:b2v_inst13|TOUT0_cout[12] data0:b2v_inst13|TOUT0_term_combout[15] data0:b2v_inst13|TF0_1_a[0] data0:b2v_inst13|TF0_0 } { 0.000ns 0.472ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.628ns 0.161ns } { 0.000ns 0.499ns 0.069ns 0.157ns 0.184ns 0.120ns 0.549ns 0.258ns 0.273ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data0:b2v_inst13|TF0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data0:b2v_inst13|TF0_0 } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.869 ns" { clock data0:b2v_inst13|TOUT0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.869 ns" { clock clock~out0 data0:b2v_inst13|TOUT0[0] } { 0.000ns 0.000ns 0.941ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.370 ns" { data0:b2v_inst13|TOUT0[0] data0:b2v_inst13|TOUT0_cout[0] data0:b2v_inst13|TOUT0_cout[1] data0:b2v_inst13|TOUT0_cout[2] data0:b2v_inst13|TOUT0_cout[7] data0:b2v_inst13|TOUT0_cout[12] data0:b2v_inst13|TOUT0_term_combout[15] data0:b2v_inst13|TF0_1_a[0] data0:b2v_inst13|TF0_0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.370 ns" { data0:b2v_inst13|TOUT0[0] data0:b2v_inst13|TOUT0_cout[0] data0:b2v_inst13|TOUT0_cout[1] data0:b2v_inst13|TOUT0_cout[2] data0:b2v_inst13|TOUT0_cout[7] data0:b2v_inst13|TOUT0_cout[12] data0:b2v_inst13|TOUT0_term_combout[15] data0:b2v_inst13|TF0_1_a[0] data0:b2v_inst13|TF0_0 } { 0.000ns 0.472ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.628ns 0.161ns } { 0.000ns 0.499ns 0.069ns 0.157ns 0.184ns 0.120ns 0.549ns 0.258ns 0.273ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}