counter.vif

用verilog实现单片机计数器 用verilog实现单片机计数器

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  counter.vlf

# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Altera

# RTL and technology files
vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -original -verilog ../../program/control0.v
vif_add_file -original -verilog ../../program/control1.v
vif_add_file -original -verilog ../../program/count_all.v
vif_add_file -original -verilog ../../program/data0.v
vif_add_file -original -verilog ../../program/data1.v
vif_add_file -original -verilog ../../program/test.v
vif_add_file -original -verilog ../../program/counter.v
vif_set_top_module -original -top counter
 
vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -translated -verilog counter.vqm
vif_set_top_module -translated -top counter