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xianshi.v
module xianshi(clk,temp_reg,seg,sl);
output[7:0]seg;
output[1:0]sl;
input clk;
input[7:0]temp_reg;
reg[7:0]seg_temp;
reg[1:0]sl_temp;
reg[3:0]disdata;
reg[12:0]count;
always@(posedge clk)
displaylcd.v
module LCDdevice(sysclk, sysrst, DI, RW, EN, CSA, CSB, RST, DATA, ctl);
input sysclk, sysrst, ctl;
output reg RW, DI, CSA, CSB, RST;
inout wire [7:0]DATA;
output wire EN;
re
stopwatch.v
module stopwatch(led_clk, led_rst, led_sel, led_seg, pause);
input led_clk, led_rst, pause;
output reg[3:0] led_sel;
output reg[7:0] led_seg;
integer countsel, countscan;
reg [3:0] led_num
calculator.v
module arith(a, b, op, result);
input [3:0] a, b;
input [2:0] op;
output [3:0] result;
reg result;
always @(a, b, op)
begin
case (op)
3'b000 : result = a + b;
3'b001 : result =
datacollect.v
module dataCollect(sysclk, rst, adda, addb, addc, start, oe,
datain, led_sel, led_seg);
input sysclk, rst;
input wire [7:0] datain;
output reg adda, addb, addc, start, oe;
output reg[3:0]
autoled.v
module LEDauto(display,rst,displayclk,scan);
input rst,displayclk;
output reg [7:0]display;
output reg [3:0]scan;
reg [3:0] singlenum[3:0];
parameter ZERO = 8'b11111100,ONE = 8'b01100000
trafficlight.v
module traffic(clk,snCar,ewCar,
snRed,snYellow,snGreen,
ewRed,ewYellow,ewGreen);
input snCar, ewCar,clk;
output reg snRed;
output reg snYellow;
output reg snGreen;
output reg ewRed;
output
timescale.v
`timescale 1ns / 10ps
timescale.v
`timescale 1ns / 1ns
timescale.v
`timescale 1ns/10ps