datacollect.v

一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型VRILOGHDL的FPGA实验

module dataCollect(sysclk, rst, adda, addb, addc, start, oe, 
		datain, led_sel, led_seg);
	input sysclk, rst;
	input wire [7:0] datain;
	output reg adda, addb, addc, start, oe;
	output reg[3:0] led_sel;
	output reg[7:0] led_seg;

	reg [3:0] counter1;
	reg [7:0] readdata;

	reg [9:0] counter2;
	reg [15:0] sum;
	reg [7:0] averdata;

 	reg [7:0] temp;
 	reg [3:0] dataout1, dataout2, dataout3;

	reg [3:0] counter3;

	parameter ZERO = 8'b11111100,ONE = 8'b01100000, TWO = 8'b11011010;
	parameter THREE = 8'b11110010, FOUR =8'b01100110;
	parameter FIVE = 8'b10110110, SIX = 8'b10111110, SEVEN =8'b11100000;
	parameter EIGHT = 8'b11111110, NINE = 8'b11110110, BLANK = 8'b00000000;


	always @(posedge sysclk or negedge rst)
	begin
		if (!rst)
		begin
			adda = 0;
			addb = 0;
			addc = 0;

			oe = 1;

			counter1 = 0;
		end
		else
		begin
			counter1 = counter1 + 1;
			case (counter1)
				3 : start = 0;
				4 : start = 1;
				5 : start = 0;
				10 : readdata = datain;
				15 : counter1 = 0;
				default : counter1 = counter1;
			endcase
		end
	end

	always @(posedge sysclk or negedge rst)
	begin
		if (!rst)
		begin
			counter2 = 0;
			sum = 0;
			averdata = 0;
		end
		else
		begin
			counter2 = counter2 + 1;
			if ((counter2%16) == 0)
				sum = sum + readdata;
			else if (counter2 > 512)
			begin
				averdata = sum / 32;
				sum = 0;
				counter2 = 0;
			end
		end
	end	 


	always @(averdata)
	begin
		temp = averdata;
		if (temp > 199)
			dataout3 = 2;
		else if (temp > 99)
			dataout3 = 1;
		else
			dataout3 = 0;
		
		temp = temp - dataout3 * 100;
		if (temp > 89)
			dataout2 = 9;
		else if (temp > 79)
			dataout2 = 8;
		else if (temp > 69)
			dataout2 = 7;
		else if (temp > 59)
			dataout2 = 6;
		else if (temp > 49)
			dataout2 = 5;
		else if (temp > 39)
			dataout2 = 4;
		else if (temp > 29)
			dataout2 = 3;
		else if (temp > 19)
			dataout2 = 2;
		else if (temp > 9)
			dataout2 = 1;
		else
			dataout2 = 0;

		temp = temp - dataout2 * 10;
		dataout1 = temp;

		if ((dataout3==0) && (dataout2==0))
		begin
			dataout3 = 10;
			dataout2 = 10;
		end
		else if (dataout3 == 0)
			dataout3 = 10;
		else
			dataout3 = dataout3;
	end


	always @(posedge sysclk or negedge rst)
	begin
		if (!rst)
		begin
			counter3 = 0;
			led_sel = 4'b0001;		
		end
		else
		begin
				if (counter3 == 4)
				begin
					counter3 = 0;
					if (led_sel == 4'b1000)
						led_sel = 4'b0001;
					else
						led_sel = led_sel << 1;
				end
				counter3 = counter3 + 1;
		end			
	end

	always @(led_sel, dataout1, dataout2, dataout3)
	begin
		case (led_sel)
			4'b0001 :
			begin
				case (dataout1)
					0 : led_seg = ZERO;
					1 : led_seg = ONE;
					2 : led_seg = TWO;
					3 : led_seg = THREE;
					4 : led_seg = FOUR;
					5 : led_seg = FIVE;
					6 : led_seg = SIX;
					7 : led_seg = SEVEN;
					8 : led_seg = EIGHT;
					9 : led_seg = NINE;
					default : led_seg = BLANK;
				endcase
			end
			4'b0010 :
			begin
				case (dataout2)
					0 : led_seg = ZERO;
					1 : led_seg = ONE;
					2 : led_seg = TWO;
					3 : led_seg = THREE;
					4 : led_seg = FOUR;
					5 : led_seg = FIVE;
					6 : led_seg = SIX;
					7 : led_seg = SEVEN;
					8 : led_seg = EIGHT;
					9 : led_seg = NINE;
					default : led_seg = BLANK;
				endcase
			end
			4'b0100 :
			begin
				case (dataout3)
					0 : led_seg = ZERO;
					1 : led_seg = ONE;
					2 : led_seg = TWO;
					3 : led_seg = THREE;
					4 : led_seg = FOUR;
					5 : led_seg = FIVE;
					6 : led_seg = SIX;
					7 : led_seg = SEVEN;
					8 : led_seg = EIGHT;
					9 : led_seg = NINE;
					default : led_seg = BLANK;
				endcase
			end
			4'b1000 :
			begin
				case (10)
					0 : led_seg = ZERO;
					1 : led_seg = ONE;
					2 : led_seg = TWO;
					3 : led_seg = THREE;
					4 : led_seg = FOUR;
					5 : led_seg = FIVE;
					6 : led_seg = SIX;
					7 : led_seg = SEVEN;
					8 : led_seg = EIGHT;
					9 : led_seg = NINE;
					default : led_seg = BLANK;
				endcase
			end
			default :
			begin
				led_seg = 1'hx;
			end
		endcase
	end

endmodule