calculator.v

来自「一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型V」· Verilog 代码 · 共 19 行

module arith(a, b, op, result);
	input [3:0] a, b;
	input [2:0] op;
	output [3:0] result;
	reg result;

	always @(a, b, op)
	begin
		case (op)
		3'b000 : result = a + b;
		3'b001 : result = a - b;
		3'b010 : result = a & b;
		3'b011 : result = a | b;
		3'b100 : result = a ^ b;
		default : result = 4'hx;
		endcase
	end
endmodule