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V 的代码
receiver.v
module receiver(
rst,
qd,
clk,
r_ram_wdb,
r_ram_wab,
r_ram_wen,
r_req,
start_read
// interrupt
);
/*** ports ***/
input rst;
input qd;
input clk;
output r_ram_wdb;
datacnt.v
module datacnt(
clk,
rst,
r_ram_rdb,
r_ram_rab,
r_req,
s_ram_wdb,
fifo_wen,
cmd,
cmdack,
addr,
datain,
dataout,
start_read,
interru
quadrature.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:04:40 05/30/2008
// Design Name:
// Modul
vgavga.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:47:17 05/29/2008
// Design Name:
// Modul
my.v
module my(
// DSP
CPLD_RESET,
MSTRB,
IOSTRB,
RW,
DS,
PS,
IS,
EA,
A,
A14,
A15,
D,
INT3,
FLASH_CE,
FLASH_RD,
FLASH_WE,
DRAM_CE,
DRAM_RD,
DRAM_WE,
PRAM_
frediv.v
//Verilog Frequency Div. 2
module frediv(clk,out);
input clk;
output out;
reg out;
always @(posedge clk)
out=(~out);
endmodule
pwm.v
module pwm(clock,keyin,pwm_out);
input clock;
input [1:0] keyin;
output pwm_out;
reg [20:0] count;
reg [9:0] pwm_count;
reg cnt_chg;
reg pwm_reg;
always @(posedge clock)
timeset.v
module timeset(
TimeSet_EN,
SW1,SW2,
hour1,hour0,
minute1,minute0,
second1,second0,
hour_set1,hour_set0,
minute_set1,minute_set0,
second_set1,se
time.v
// Copyright (C) 1991-2004 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any
stopwatch.v
module stopwatch(clk1,clk2,EN,F_out);
output F_out;
input EN;
input clk1,clk2;
reg F_out;
always @(EN,clk1,clk2)
begin
case(EN)
1'b0: F_out