time.v

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

module time(
	CLK,
	Timepiece_EN,
	TimeSet_EN,
	SW1,
	SW2,
	Day_EN,
	hour_0,
	hour_1,
	minute_0,
	minute_1,
	second_0,
	second_1,
	TimeSet_disp_drive
);

input	CLK;
input	Timepiece_EN;
input	TimeSet_EN;
input	SW1;
input	SW2;
output	Day_EN;
output	[3:0] hour_0;
output	[3:0] hour_1;
output	[3:0] minute_0;
output	[3:0] minute_1;
output	[3:0] second_0;
output	[3:0] second_1;
output	[2:0] TimeSet_disp_drive;

wire	[3:0] SYNTHESIZED_WIRE_18;
wire	[3:0] SYNTHESIZED_WIRE_19;
wire	[3:0] SYNTHESIZED_WIRE_2;
wire	[3:0] SYNTHESIZED_WIRE_3;
wire	[3:0] SYNTHESIZED_WIRE_20;
wire	[3:0] SYNTHESIZED_WIRE_21;
wire	[3:0] SYNTHESIZED_WIRE_6;
wire	[3:0] SYNTHESIZED_WIRE_7;
wire	[3:0] SYNTHESIZED_WIRE_22;
wire	[3:0] SYNTHESIZED_WIRE_23;
wire	[3:0] SYNTHESIZED_WIRE_10;
wire	[3:0] SYNTHESIZED_WIRE_11;





timepiece_main	b2v_inst1(.CLK(CLK),
.Timepiece_EN(Timepiece_EN),.day_EN(Day_EN),.hour0(SYNTHESIZED_WIRE_18),.hour1(SYNTHESIZED_WIRE_19),.minute0(SYNTHESIZED_WIRE_20),.minute1(SYNTHESIZED_WIRE_21),.second0(SYNTHESIZED_WIRE_22),.second1(SYNTHESIZED_WIRE_23));

time_mux	b2v_inst2(.TimeSet_EN(TimeSet_EN),
.hour0(SYNTHESIZED_WIRE_18),.hour1(SYNTHESIZED_WIRE_19),.hour_set0(SYNTHESIZED_WIRE_2),.hour_set1(SYNTHESIZED_WIRE_3),.minute0(SYNTHESIZED_WIRE_20),.minute1(SYNTHESIZED_WIRE_21),.minute_set0(SYNTHESIZED_WIRE_6),.minute_set1(SYNTHESIZED_WIRE_7),.second0(SYNTHESIZED_WIRE_22),.second1(SYNTHESIZED_WIRE_23),.second_set0(SYNTHESIZED_WIRE_10),.second_set1(SYNTHESIZED_WIRE_11),.hour_0(hour_0),.hour_1(hour_1),.minute_0(minute_0),.minute_1(minute_1),.second_0(second_0),.second_1(second_1));

timeset	b2v_inst3(.TimeSet_EN(TimeSet_EN),
.SW1(SW1),.SW2(SW2),.hour0(SYNTHESIZED_WIRE_18),.hour1(SYNTHESIZED_WIRE_19),.minute0(SYNTHESIZED_WIRE_20),.minute1(SYNTHESIZED_WIRE_21),.second0(SYNTHESIZED_WIRE_22),.second1(SYNTHESIZED_WIRE_23),.disp_drive(TimeSet_disp_drive),.hour_set0(SYNTHESIZED_WIRE_2),.hour_set1(SYNTHESIZED_WIRE_3),.minute_set0(SYNTHESIZED_WIRE_6),.minute_set1(SYNTHESIZED_WIRE_7),.second_set0(SYNTHESIZED_WIRE_10),.second_set1(SYNTHESIZED_WIRE_11));


endmodule