timeset.v

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

module timeset(
			   TimeSet_EN,
			   SW1,SW2,
			   hour1,hour0,
			   minute1,minute0,
			   second1,second0,
			   hour_set1,hour_set0,
			   minute_set1,minute_set0,
			   second_set1,second_set0,
			   disp_drive			    
			   );
output [3:0] hour_set1,hour_set0;
output [3:0] minute_set1,minute_set0;
output [3:0] second_set1,second_set0;
output [2:0] disp_drive;
input  TimeSet_EN;
input  SW1,SW2;
input  [3:0] hour1,hour0;
input  [3:0] minute1,minute0;
input  [3:0] second1,second0;

reg [3:0] hour_set1,hour_set0;
reg [3:0] minute_set1,minute_set0;
reg [3:0] second_set1,second_set0;
reg [2:0] disp_drive;

//初始化
initial
begin 
  hour_set1   <= hour1;
  hour_set0   <= hour0;
  minute_set1 <= minute1;
  minute_set0 <= minute0;
  second_set1 <= second1;
  second_set0 <= second0;
end

always @(posedge SW1) 
//手动设置使能	
begin
  if(TimeSet_EN == 1'b1)
    begin
	  if(disp_drive < 3'b101)
	    disp_drive <= disp_drive + 3'b1;
	  else
	    disp_drive <= 3'b0;
	end
end

always @(posedge SW2)
begin
  case(disp_drive)
    //小时的高位
    3'b000: begin
	          if(hour_set1 < 4'b0010)
	            hour_set1 <= hour_set1 + 4'b1;
	          else
		        hour_set1 <= 4'b0;
    	    end
    //小时的低位
    3'b001: begin
   		      if(hour_set0 < 4'b1001)
			    hour_set0 <= hour_set0 + 4'b1;
			  else
			    hour_set0 <= 4'b0;
    	    end
    //分的高位
	3'b010: begin
			  if(minute_set1 < 4'b0101)
			    minute_set1 <= minute_set1 + 4'b1;
			  else
			    minute_set1 <= 4'b0;
    	    end 
    //分的低位
	3'b011: begin
		      if(minute_set0 < 4'b1001)
		        minute_set0 <= minute_set0 + 4'b1;
		      else
		        minute_set0 <= 4'b0;
    	    end
    //秒的高位
	3'b100: begin
			  if(second_set1 < 4'b0101)
			    second_set1 <= second_set1 + 4'b1;
			  else
			    second_set1 <= 4'b0;
    	    end 
    //秒的低位
	3'b101: begin
		      if(second_set0 < 4'b1001)
		        second_set0 <= second_set0 + 4'b1;
		      else
		        second_set0 <= 4'b0;
    	    end
    default:begin
            end
  endcase
end

endmodule